ASIC DESIGN ENGINEER JOB DESCRIPTION

An ASIC Design Engineer who cannot close timing on a complex SoC block forces respins, and a respin at advanced process nodes costs millions and adds months to a product schedule. This role owns RTL design, micro-architecture definition, and front-end integration for digital and mixed-signal blocks within a semiconductor product team. The work demands fluency in clock domain crossing, low-power methodology, and the full synthesis-to-netlist flow across multi-voltage SoC environments. Tape-out success, not just functional correctness, is the standard.

As the ASIC Design Engineer, you own the RTL specification, implementation, and front-end integration of one or more SoC blocks, directly determining whether a chip meets its power, performance, and area targets before tape-out. You work within a cross-functional team spanning physical design, verification, firmware, and systems engineering, with scope that extends from micro-architecture definition through post-silicon bring-up.

Career Impact: Owning a successful SoC tape-out as the RTL lead establishes a verifiable track record that commands premium market value in the semiconductor industry's most competitive design centers.

Business Impact: When RTL blocks close timing cleanly and netlists are delivered with zero lint violations, downstream physical design and verification teams can execute on schedule; any slip here delays the entire product release.

Growth Opportunity: Engineers who master multi-voltage power intent, CDC closure, and micro-architecture trade-off analysis are well positioned to advance into SoC Architect or Design Lead roles with ownership of larger subsystems.

• Architect and implement RTL for assigned digital blocks, targeting power, performance, and area goals defined in the micro-architecture specification.
• Define synthesis constraints and drive timing closure in collaboration with the physical design team across multi-clock, multi-voltage domains.
• Integrate IP blocks and sub-systems designed by internal and external teams, validating interfaces against AMBA and other protocol specifications.
• Support design verification by authoring self-checking test benches and providing feedback on coverage closure to the DV team.
• Execute front-end integration flows including lint, CDC, RDC, logic equivalence checking, and ECO delivery.
• Conduct post-silicon bring-up and debug of owned blocks, root-causing simulation failures and correlating them to lab observations.
• Review and author micro-architecture specifications, participating in design reviews with systems, firmware, and program stakeholders.
• Mentor junior engineers on RTL coding standards, design methodology, and front-end flow automation.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent work experience.
• 5 or more years of ASIC RTL design experience, with demonstrated ownership of a complete SoC block from specification through netlist delivery.
• Proficiency in HDL coding in Verilog or SystemVerilog, including synthesis constraints, clock domain crossing, and low-power design techniques.
• Experience executing front-end flows covering synthesis, lint, CDC analysis, timing closure, and logic equivalence checking.
• Hands-on knowledge of IP integration within SoC environments, including sub-system interfaces and protocol-level design.
• Scripting proficiency in at least two languages used for design automation, flow management, or data analysis.
• Experience with post-silicon bring-up, lab debug methodology, or FPGA-based prototyping for design validation.
• Strong written and verbal communication skills, with the ability to produce and review detailed technical specifications.

• Advanced degree (MS or PhD) in Electrical or Computer Engineering, supporting deeper micro-architecture trade-off analysis.
• Experience with formal verification methods, including property checking and equivalence verification at block or sub-system level.
• Familiarity with power intent specification using UPF and multi-voltage domain implementation within complex SoC designs.
• Background in hardware security primitives, cryptographic block integration, or ISO-26262 functional safety collateral for semiconductor products.

• RTL-to-netlist delivery rate, measured by the percentage of assigned blocks reaching synthesis signoff on the first submission.
• Timing closure cycle count, tracking how many ECO iterations are required before a block meets setup and hold targets.
• CDC and lint violation density at integration handoff, targeting zero unwaived errors per delivered netlist.
• Post-silicon debug turnaround time, measured in days from lab failure report to root-cause identification on owned blocks.
• Micro-architecture specification review acceptance rate, reflecting how often authored specs proceed without significant rework.
• Typical tools: RTL simulation (commonly VCS or Xcelium); synthesis and STA (commonly Design Compiler or Genus/Tempus); lint and CDC (commonly Spyglass or Ascent/Meridian); scripting (Tcl, Python, Perl).

• Base Salary Range: $130,000 to $185,000 per year
• Bonus: Annual performance bonus, typically 8 to 15% of base salary
• Equity: RSU grants common at mid-to-senior levels; refreshes standard at larger semiconductor firms
• Health Benefits: Medical, dental, and vision coverage; employer contributions standard
• PTO: 15 to 20 days annually; additional sick leave and company holidays
• Common Perks: On-site or remote lab access, conference and continuing education funding, relocation assistance

Figures are estimates based on general US market benchmarks and may be outdated. Adjust based on location, company size, and seniority level.

Background checks are a standard condition of employment, and all offers are contingent on successful completion. Work authorization to work in the United States is required; sponsorship availability varies by employer. All qualified applicants will receive equal consideration for employment without regard to race, color, religion, sex, national origin, age, disability, veteran status, or any other characteristic protected under applicable federal, state, or local law. Reasonable accommodations are available to applicants and employees with disabilities upon request.

The ASIC Design Engineer owns RTL development and architecture for High Bandwidth Interface PHY IP and test chips, working within Synopsys's digital design team alongside verification, controller, and lab teams. Delivering first-pass silicon quality, the role shapes the full RTL-to-GDS flow while engaging directly with customers to resolve technical issues and mentoring junior engineers.

Key Responsibilities

• Develop specifications, architecture, and RTL for High Bandwidth Interface PHY IP and test chips.
• Define synthesis design constraints and resolve STA and gate-level simulation issues.
• Collaborate with the verification team and review verification plans against specifications.
• Collaborate with controller and sub-system design and verification teams.
• Follow RTL-to-GDS flow and coordinate with other teams during logic implementation phases.
• Collaborate with the lab team to debug silicon issues related to logic design.
• Lead project activities when required.
• Engage directly with customers to resolve technical issues related to RTL.
• Contribute to digital flow development and train junior RTL engineers.

Required Qualifications

• Bachelor's, Master's, or PhD in Electronics Engineering or Telecommunications.
• 5+ years of experience in RTL design for ASIC or PHY IP.
• Experience in Analog Mixed Signal IP design.
• Proficiency with VCS, Verdi, Spyglass, or similar tools.
• Solid knowledge of clock domain crossing.
• Strong scripting skills in Perl, Tcl, and Python.
• Familiarity with APB and JTAG protocols.
• Proficiency in English, both spoken and written.
• Strong communication skills, both verbal and written.
• Results-oriented, highly responsible, and self-motivated with enthusiasm for technology and problem-solving.

Embedded within the ASIC development team, the ASIC Design Engineer builds and maintains the CAD/EDA tool environment that enables analog, digital, and mixed-mode IC design flows across a multi-user Linux cluster infrastructure. Working closely with IT, security, and major EDA vendors, this role ensures optimized toolsets and standardized design practices that keep the entire engineering team productive.

Core Functions

• Build and maintain the design environment to support ASIC development team operations.
• Maintain up-to-date organization of CAD/EDA tools, process design kits, version-controlled repositories, design libraries, IP, and outside-vendor libraries.
• Work with IT and security teams on Linux-based cluster configuration for installation and maintenance of CAD/EDA tools from major vendors.
• Integrate designs in a multi-user environment via process and design management tools.
• Organize work directories, system shell scripts, tool scripts, physical and functional design verification decks, and solutions for tool interoperability.
• Set up and maintain environments for AI and machine learning modeling and simulations, including integration with digital and mixed-mode IC design flows.
• Set up and maintain other ECAD tools supporting ASIC design efforts, including physical-level device simulations, model extraction, calculus, and data presentation.
• Interact with major vendors to provide an optimized toolset, and organize tools, process design kit workshops, design technique trainings, and standardized design practice monitoring.
• Participate in ASIC designs, including analog, digital, mixed-mode, and functional verification, as required.

Qualifications & Experience

• Bachelor's degree in an engineering discipline or closely related field.
• Master's degree in an engineering discipline or closely related field.
• Minimum three years of related work experience.
• Familiarity with ASIC design processes, flows, and CAD/EDA tool interoperability.
• Knowledge of SKILL, Tcl/Tk, ASSURA, and Calibre DRC/LVS verification deck syntax.
• Knowledge of operating system shell scripting or other scripting languages, including Perl and Python.
• Ability to execute analog and/or digital ASIC design flows for performing design tasks.
• Knowledge of back-end ASIC design elements, including layout, physical verification, and design verification.
• Ability to guide the ASIC team in specific areas.

Reporting to the instrumentation division engineering lead, the ASIC Design Engineer designs analog, digital, and mixed-mode ASICs for instrumentation instruments using Cadence and similar CAD/EDA environments. Partnering with cross-functional teams on machine learning, artificial intelligence, and quantum science initiatives, this role translates theoretical analyses into validated silicon through full-custom and automated physical design implementation.

Primary Duties

• Design analog, digital, or mixed-mode ASICs for instrumentation division instruments.
• Design circuit networks using schematic entry and layout tools in a Cadence or similar CAD/EDA environment.
• Develop models of circuit networks and system components in hardware description languages for analog and digital modeling toward synthesis with time-enclosed place and route.
• Perform full-custom or automated physical ASIC design implementation from RTL code.
• Build analog or digital test benches and carry out mixed analog and digital circuit simulations.
• Execute physical and functional circuit and system verification.
• Develop design specifications based on theoretical analyses and application needs.
• Prepare technical documentation and carry out test-board designs and laboratory testing.
• Participate in co-designing ASICs and sensors with Technology CAD tools, collaborating on machine learning, artificial intelligence, and quantum science initiatives.

Skills & Qualifications

• Bachelor's degree in an engineering discipline or closely related field.
• Advanced degree (MSc) in an engineering or physical sciences discipline or closely related field.
• Three or more years of related work experience.
• Familiarity with ASIC design processes, flows, and CAD/EDA tool interoperability.
• Knowledge of readout integrated circuits for radiation sensors, including signal processing, signal filtering, signal conversion, data transmission, and high-speed electronics.
• Proficiency with SKILL, Tcl/Tk, ASSURA, and Calibre DRC/LVS verification deck syntax, as well as operating system shell scripting or other scripting languages, including Perl and Python.
• Ability to execute analog and/or digital ASIC design flows for performing design tasks.
• Ability to work with diverse group members in a multi-user process and design-managed environment.

Sitting at the intersection of hardware architecture and silicon delivery, the ASIC Design Engineer leads cross-functional SoC development by micro-architecting and designing hardware accelerator IP in Verilog/SystemVerilog and defining ASIC design methodologies. Operating across software, physical design, and stakeholder teams, this role drives end-to-end tape-outs of major SoC blocks with optimized power, performance, and area.

Duties

• Micro-architect and design hardware accelerator IP in Verilog/SystemVerilog HDL.
• Define and own ASIC design methodologies.
• Lead cross-functional SoC development activities.
• Work with stakeholders and functional teams to ensure delivery of high-quality IP to SoC product teams.
• Provide technical leadership through mentorship and strong teamwork.
• Develop using modern programming languages, open-source technologies, and Linux.
• Apply gate-level testing and multi-clock design practices, including CDC.
• Work with software teams to define the HW/SW interface, including control/status registers and error handling.
• Work closely with physical design teams to develop highly optimized ASICs with excellent power, performance, and area.
• Define micro-architecture from architecture guidelines and model analysis.

Requirements

• BS degree or higher in Electrical Engineering, Computer Engineering, or Computer Science.
• 5+ years of practical semiconductor ASIC design experience, including owning end-to-end design of major SoC blocks.
• Demonstrated successful tape-outs as owner of a major design block.
• Experience writing HDL in Verilog/SystemVerilog and understanding architectural models and algorithms in C/C++.
• In-depth knowledge of CPU, DSP, or programmable accelerators, and experience with RISC-V.
• Experience with synthesis, timing, design constraints, and early power analysis.
• Experience in RTL coding, debug, and performance/power/area analysis and trade-offs, including timing analysis and working with physical design teams to close timing.
• SoC bring-up and post-silicon validation experience.
• Experience in architecture and system engineering, and working with internal and external partners.
• Proficiency in design methodologies and EDA tools.

A key member of the front-end design services team, the ASIC Design Engineer supports customer designs through all phases of ASIC execution, performing microarchitecture, RTL design, synthesis, and timing closure to meet product performance requirements. Collaborating across verification, physical design, FPGA, firmware, and global teams, this role ensures project milestone deadlines are met on complex SoC projects from start to finish.

Functions

• Work with customers, vendors, and internal teams across all phases of ASIC execution.
• Support customer designs through all phases of ASIC execution.
• Perform tasks related to microarchitecture, RTL design, synthesis, and timing closure to ensure designs meet product performance requirements.
• Ensure project milestone deadlines are met.
• Work effectively with internal teams, including verification, physical design, FPGA, and firmware teams, including global teams.

Experience & Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• Hands-on ASIC front-end design experience, ideally in design services environments.
• Experience with major SoC projects from start to finish.
• Experience with micro-architecture at module, sub-system, and chip level, and digital design of complex modules and sub-systems with a solid understanding of clock-domain crossings.
• Experience with integration of IPs, modules, and sub-systems designed by internal and external teams, and experience using AMBA bus protocols.
• Experience with SystemVerilog, lint and CDC analysis, timing analysis, debug skills, and customer support.
• Experience in at least a few of the following: CPU (preferably ARM), GPU, or DSP; low-power design and verification; peripheral interfaces such as CSI, I3C, USB, and PCIe; FPGA.
• Experience dealing with international teams in a small company environment.
• Strong interpersonal skills, with the ability to meet stringent deadlines and project timelines.

Designing safety mechanisms and leading fault simulation campaigns, the ASIC Design Engineer delivers ISO-26262-compliant ASIC solutions by conducting functional safety design reviews, performing FMEDA analysis on RTL designs including third-party IP, and generating required safety collateral. Based within an automotive semiconductor program, this role directly enables diagnostic coverage demonstration and ISO-26262 certification of complex devices.

Accountabilities

• Conduct Functional Safety design reviews and generate DFMEA documents.
• Analyze RTL designs, including third-party IP, perform FMEDA analysis, and generate FMEDA documents.
• Qualify ASIC Design EDA tools.
• Participate in and contribute to the System Functional Safety Plan and to the negotiation of DIAs.
• Create, evaluate, and design ASIC Safety Mechanisms.
• Lead Fault Simulation Campaigns to uncover faults and demonstrate diagnostic coverage.

Technical Qualifications

• 5+ years of RTL design experience using SystemVerilog.
• In-depth knowledge of ISO-26262 as it relates to ASIC design and automotive reliability standards.
• Previous experience creating DFMEAs, FMEDAs, and other ISO-26262 collateral documents.
• Leadership experience obtaining ISO-26262 certification of a complex semiconductor device.
• Previous experience conducting a Fault Simulation Campaign.
• Previous experience with ISO-26262-related software tools for management and tracking, such as Jama.
• Previous experience with RTL-level functional safety estimation tools.
• Previous experience generating a Functional Safety Plan and/or Functional Safety Manual.

As the ASIC Design Engineer, this role authors micro-architecture specifications and architects complex RTL designs while collaborating with physical design, verification, and vendor teams to optimize power and achieve coverage closure. The design team relies on this work to deliver silicon bring-up, post-silicon validation, and lab diagnostics that resolve simulation and customer failures from root cause.

Activities

• Author micro-architecture specifications and participate in specification and test plan reviews.
• Architect and implement complex RTL designs.
• Collaborate with the physical design team to resolve implementation and timing issues and to optimize power.
• Scope third-party IP requirements and solicit vendors.
• Analyze code coverage and provide feedback to the verification team to achieve coverage closure.
• Triage, debug, and root-cause simulation, software bring-up, and customer failures.
• Perform diagnostic and post-silicon validation tests in the lab.
• Mentor and coach colleagues.

Position Requirements

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• 5+ years of ASIC design experience.
• Experience with low-power design and clock domain crossings.
• Excellent Verilog/SystemVerilog programming skills.
• Proficiency in physical design, implementation, and synthesis constraints, and strong debug skills.
• Understanding of SoC and/or networking ASICs.
• Scripting experience in Python, Perl, TCL, and shell programming.
• Good written and verbal communication skills.
• Collaborative and team-focused with a commitment to learn and grow.

ASIC Design Engineer shapes the architecture and implementation of hardware accelerators that process sensor data and system compute workloads, working alongside researchers to identify acceleration needs and integrating embedded processors and DSPs. The work directly supports the creation of simulation-validated digital designs through power, area, and performance trade-off analyses and toolchain development.

Operational Focus

• Work with researchers to identify compute acceleration needs.
• Specify, architect, and design hardware accelerators that process sensor data and other system compute workloads.
• Perform power, area, and performance trade-off analyses of digital designs.
• Create and run software that tests digital designs in simulation and bring-up.
• Integrate embedded processors and DSPs and develop toolchains.

Knowledge Skills & Abilities

• BS degree in Computer Engineering or equivalent practical experience.
• Master's or PhD degree in Engineering.
• 6+ years of industry experience with Verilog and SystemVerilog RTL digital microarchitecture.
• Extensive experience with C/C++.
• Experience with High-Level Synthesis (HLS), including Catapult and/or Vivado HLS.
• Experience with the full digital design verification cycle, from spec through bring-up, including performance and power validation and formal verification.
• Knowledge of computer architecture, on-chip communication buses, and industry-standard protocols such as PCIe, DDR, Ethernet, and NoCs.
• Experience with machine learning and other high-performance compute elements.

The ASIC Design Engineer produces chip specifications and derives silicon specifications from software and hardware systems, defining chip function partitions, interfaces, and system-level testing criteria for design and verification teams. Working across hardware, platform, and software stakeholders on networking and image signal processing pipelines, this role validates design concepts through performance tests and drives hardware system design reviews.

Key Deliverables

• Define chip specifications and derive silicon specifications from software and hardware systems.
• Define chip function partitions and interfaces for the design team.
• Define system-level testing criteria for the verification team.
• Provide detailed documentation for hardware, platform, and software teams.
• Run performance tests to validate the design concept.
• Select hardware parts and vendors.
• Drive design reviews of hardware systems and related software systems.

Professional Experience

• BS or MS in Engineering or a related discipline.
• 10+ years of chip design and SoC architecture experience.
• Proven success in SoC chip architecture definition and implementation.
• Strong background in networking and/or image processing, with extensive knowledge of image signal processing (ISP) pipelines.
• Experience in implementing digital signal processing algorithms.
• Hands-on experience with PCIe, DDR, Ethernet, and peripherals.
• Excellent communication, documentation, and learning skills.

Reporting to senior engineering leadership, the Sr. ASIC Design Engineer leads architecture and micro-architecture of the chip control unit for Machine Learning ASICs, owning the top-level netlist and driving IP integration, CDC, clocking, power management, and security solutions. Partnering with system software teams on boot code and firmware, this role directly advances silicon bring-up quality for high-performance AI chips.

Areas of Ownership

• Lead architecture, micro-architecture, and design of the chip control unit for Machine Learning ASICs.
• Own the top-level netlist and lead selection and integration of IP, CDC, clocking, and resets.
• Architect, implement, and verify power management techniques, including multiple voltage domains and isolation cell insertion.
• Architect and implement security solutions.
• Collaborate with the system software team on boot code and firmware development.
• Guide and review verification of owned blocks.
• Participate in silicon bring-up for owned blocks.
• Coordinate design activities for blocks with software and systems teams.

Background & Experience

• BS in Electrical Engineering, Computer Engineering, or a related degree; advanced degrees (MS, PhD) a plus.
• 6+ years of industry experience in high-speed complex ASIC/SoC design.
• Expert-level knowledge in control and boot subsystems of complex, high-performance processors, GPUs, or application processors.
• Expert knowledge in clock and reset design and implementation of complex ASIC power management systems with UPF.
• Expert proficiency in microcontroller peripherals, including I2C/SMB, SPI, UART, and ADC, and experience with multiple clock domains and asynchronous interfaces.
• Experience with all stages in the ASIC design flow, including emulation, prototyping, DFT, synthesis, timing analysis, floorplanning, ECO, bring-up, lab debug, and ATE test development.
• Experience in integrating ASIC IP into SoC, with experience in security and bootloaders a plus.
• Experience with industry-standard EDA tools from Cadence, Synopsys, or Mentor.
• Expertise in developing firmware and system management software for high-performance processors is a plus.
• Experience in designing tools and scripts for creating control and status register maps a plus.
• Proficient coding skills in Verilog or SystemVerilog.

Embedded within a hardware security IP team, the ASIC Design Engineer develops robust IP products covering micro-architecture design, RTL implementation, and back-end flows, while representing the hardware team in cross-functional forums with program managers, product managers, and sales teams. Working closely with cross-site teams to improve ASIC flows and methodologies, this role advances the delivery of security IP integrated across SoCs and FPGAs.

Role Responsibilities

• Work with system architects and software architects to define hardware architecture specifications for IP products.
• Own major blocks of IP design and produce robust IP products, including micro-architecture design, RTL implementation, and back-end flows.
• Provide technical leadership in the implementation and development of hardware security products.
• Represent the hardware team in cross-functional forums involving program managers, product managers, and sales teams.
• Develop and produce collateral for easy integration of IP products into SoCs and FPGAs.
• Develop and improve existing ASIC flows and methodologies in collaboration with other team members.

Qualifications & Experience

• BS or MS degree in Electrical or Computer Engineering or a closely related field.
• 10+ years of experience as an ASIC/SoC design engineer or in a related field.
• Strong experience in digital design, including data and control paths, interfaces, interconnects, and CPU.
• Experienced at producing highly detailed architecture and micro-architecture specifications for complex blocks, sub-systems, or SoCs and delivering high-quality designs.
• Experience with formal verification tools and working understanding of verification methodologies.
• Experience in creating or optimizing designs for FPGA, including implementation on FPGA platforms and bit file creation for FPGA emulation and acceleration.
• Familiarity with IP integration, IP core delivery, and handoff issues.
• Experience in leading IP development, improving methodology, and working with cross-site teams.
• Knowledge of industry-standard interfaces and experience in data, software, and/or network security, including cryptography.
• Strong written and verbal communication skills in English, with strong problem-solving skills and attention to detail.

Reporting to the systems team lead, the ASIC Design Engineer carries primary responsibility for RTL design on Mixed Signal ASICs, developing detailed specifications for digital functions and implementing them in Verilog RTL through unit-level testing and full design integration. Partnering with physical design and DV teams on STA, power, logical issues, and self-checking tests, this role refines the design flow from lint and CDC through synthesis and ECO to closure.

Job Functions

• Work with the systems team to understand top-level requirements.
• Develop detailed specifications for digital functions.
• Implement digital functions in Verilog RTL to specification.
• Perform unit-level testing on RTL functions.
• Support the DV team by writing self-checking tests as required.
• Support all design integration activities, including lint, CDC, synthesis, and ECO.
• Work with the physical design team on STA, physical, power, and logical issues.

Skills & Qualifications

• Experience in setting up power distribution architecture, power intent specification, and validation methodology.
• Experience in defining methodology and creating infrastructure to support FPGA-based prototyping.
• Experience in low-power design.
• Knowledge of best practices for implementation of digital logic.
• Understanding of the digital design flow, including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, gate-level simulation, and equivalence checking.
• Proficiency in industry-standard RTL design and synthesis tools, as well as extraction and STA methodology and tools.
• Flow automation scripting skills in Perl/Python, Tcl, and shell scripts.
• Understanding of design verification and the ability to write self-checking test suites.
• Experience in ASIC test methodology, including scan insertion, memory BIST, and test pattern generation.

As the ASIC Design Engineer, this role designs, develops, integrates, and tests FPGA firmware for network security appliances covering cryptographic algorithms, interface protocols, and security features, working alongside software, firmware, and systems engineers to meet product requirements. The network security team relies on this work to deliver simulation-verified, synthesis-optimized firmware through Xilinx and Altera FPGA design flows with strong reusability standards.

What You'll Do

• Design, develop, integrate, and test FPGA firmware for network security appliances, including cryptographic algorithms, low- and high-speed interface protocols, management interfaces, and security features.
• Work closely with software, firmware, and systems engineers to ensure firmware implementations meet product requirements.
• Perform design entry in VHDL and/or Verilog and functional verification with a strong emphasis on reusable and maintainable designs.
• Conduct comprehensive unit testing of implementations via simulation and emulation.
• Perform logic synthesis, static timing analysis, and place and route within Xilinx or Altera FPGA design flows.
• Support software and system integration and test efforts.
• Resolve issues found during engineering test, accounting for program and schedule risk when identifying the best solution.

Requirements

• Bachelor of Science in Electrical Engineering, Computer Science, or a related discipline, or equivalent experience.
• Minimum 2 years of ASIC or FPGA design experience.
• Familiarity with Xilinx UltraScale+ MPSoC architecture.
• Familiarity with Modelsim/Questa for simulation and code coverage analysis.
• Familiarity with Xilinx and/or Altera FPGA design flows for synthesis, place and route, and timing analysis.
• Familiarity with Ethernet, including MACs, PHYs, and protocols.
• Ability to derive firmware requirements from system-level requirements and design specifications.
• Strong organization, coordination, planning, and teaming skills, with good documentation skills.

The ASIC Design Engineer develops wireless modem and DSP silicon solutions for the latest CMOS generation technologies, collaborating with wireless system teams to implement architecture from system specification through RTL, timing, and power optimization to chip-level validation. Serving as a contributor to UVM and SystemC system-level verification, this role directly supports first-time-right silicon outcomes that optimize customer throughput, latency, and power within cost constraints.

Day-to-Day Responsibilities

• Implement wireless system architecture in silicon, from system specification to chip specification to RTL, through timing and power optimization to chip-level validation.
• Develop solutions optimizing customer experience in throughput, latency, and availability while meeting power and cost constraints.
• Drive high-quality designs for first-time-right silicon solutions while meeting power objectives.
• Create standalone verification test benches to verify block correctness.
• Work with the verification team and participate in system-level verification using UVM, SystemC, and DPI-C test benches.
• Ensure blocks meet DFT, timing, and power targets by working closely with the implementation team.
• Drive trade-off analysis to optimize customer experience and resources, including costs, power, and spectrum.

Education & Experience

• Bachelor's degree in Electrical or Communications Engineering or a related field, or equivalent experience.
• Master's or PhD degree in Electrical or Communications Engineering.
• 5+ years of experience in digital design, preferably in communication systems.
• Familiarity with UVM and MATLAB.
• Ability to write assertions and exposure to formal verification.

A key member of the front-end SoC integration team, the ASIC Design Engineer oversees all front-end ASIC/SoC design activities, including lint, CDC, RDC, constraint generation, memory generation, logic equivalence, and power analysis for complex multi-clock, multi-voltage SoCs. Collaborating across physical and synthesis flow teams using TCL, Python, and JavaScript/TypeScript automation, this role ensures full-chip timing closure and low-power flow integrity.

Scope of Work

• Work on all front-end aspects of ASIC/SoC designs, including lint, CDC, RDC, constraint generation, constraint promotion and demotion, memory generation, logic equivalence, power analysis, and ECO.
• Participate in full-chip timing constraints for a complex, multi-clock, multi-voltage SoC, including integration of complex IP constraints, constraints partitioning, IO timing budgeting, and overall SDC generation.
• Assist with physical-aware synthesis flows and low-power flows, including multi-Vt, multi-voltage synthesis, and power gating insertion in complex SoCs.
• Develop and maintain fully automated scripts and flows using TCL, CSH, Python, and JavaScript/TypeScript.

Experience & Qualifications

• BS in Electrical or Computer Engineering with at least 5 years of experience.
• MS in Electrical Engineering with at least 3 years of experience.
• Experience with Synopsys EDA tools, including Design Compiler, PrimeSuite, Formality ECO, PrimePower, and Integrator.
• Experience with Real Intent EDA tools, including Ascent Lint, Meridian CDC, and Meridian RDC.
• Experience with the ExcelliCon Suite or similar constraint generation tools.
• Proficiency in scripting in multiple languages, including TCL, CSH, Python, and JavaScript/TypeScript.

ASIC Design Engineer advances the architecture and RTL implementation of next-generation data center accelerators for Machine Learning computation, defining micro-architecture specifications and taking ownership of one or more modules through PPA closure. The work directly supports data center ML acceleration teams by converging functionality and design quality from concept to silicon across design methodology, libraries, and code review.

Work Activities

• Define micro-architecture specifications.
• Take ownership of one or more modules and implement RTL.
• Converge functionality and PPA of the design.
• Create simple test benches and debug complex logic simulations.
• Contribute to design methodology, libraries, and code review.

Technical Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• Master's degree or PhD in Electrical Engineering or Computer Science.
• 2 years of experience in ASIC hardware.
• Experience with one or more successful ASIC products from concept to silicon.
• Experience in logic design and functional and PPA closure.
• Experience with engineering practices, including code review, testing, refactoring, and computer architecture.
• Solid understanding of computer architecture, memory subsystem architecture, and/or power management logic.
• Knowledge of machine learning.

The ASIC Design Engineer creates and integrates automotive Time-Sensitive Network Gigabit Ethernet MAC into safety-critical silicon, developing block- and system-level RTL to meet synthesis, physical, DFT, power, and Functional Safety requirements, while coordinating with IP vendors, physical design, verification, and systems teams. This role directly enables automotive network architecture delivery by leading emulation platform bring-up and ensuring all use cases meet ISO-26262 safety targets.

Performance Expectations

• Configure and integrate an automotive Time-Sensitive Network (TSN) Gigabit Ethernet MAC.
• Serve as the technical interface with the IP vendor to address all issues arising with the IP.
• Work with systems and software teams to ensure all configurations and automotive use cases are addressed.
• Specify and document the overall network architecture.
• Develop block and system-level RTL to meet synthesis, physical, DFT, and power goals.
• Develop block architecture and RTL to meet Functional Safety requirements of the chip.
• Collaborate with the physical design team to meet overall physical design targets.
• Work with the verification team to develop and review test plans for assigned blocks.
• Work with systems and software teams on emulation platforms and lead the bring-up of assigned blocks.

Skills & Qualifications

• BSEE or equivalent degree.
• 5 years of industry experience in digital design.
• Prior experience with embedded Ethernet implementations, preferably automotive.
• Experience in RTL design with Verilog/SystemVerilog.
• Understanding of standard IC design methodology, including simulation, synthesis, timing closure, and DFT.
• Ability to work collaboratively with a verification team.

Embedded within the system IP team, the ASIC Design Engineer executes RTL design and synthesis of system IP blocks, including SDMA micro-architecture implementation, targeting high-frequency, low-power design through front-end integration flows and timing closure with physical design teams. Collaborating with verification engineers and RTL owners on debugging and post-silicon firmware, this role coordinates the delivery of netlists with consistently good quality.

Core Responsibilities

• Lead RTL design and synthesis of system IP, including IP architecture design, to achieve high-frequency, low-power design targets.
• Run front-end integration flows, including synthesis, lint, and DFT, and deliver netlists with good quality.
• Work with RTL owners and the physical design team on timing closure and report checks.
• Implement RTL for assigned system IP blocks per specification.
• Work with verification engineers on debugging.
• Perform post-silicon debugging and firmware development.

Experience & Qualifications

• Experience in ASIC or FPGA projects.
• Experience in synthesis, timing analysis, and formal verification.
• Familiarity with front-end EDA tools and flows.
• Proficiency in Verilog design.
• Advanced programming knowledge in Perl, Tcl/tk, and Makefiles.