ASIC VERIFICATION ENGINEER JOB DESCRIPTION

Verification engineering is how a chip proves it works before fabrication. That single-sentence mission sits at the center of every SoC program, where the cost of a post-silicon escape far exceeds the cost of a missed schedule. An ASIC Verification Engineer owns the test plan, the testbench architecture, and the coverage closure decisions that determine whether an RTL freeze can be called with confidence. The role demands deep fluency in constrained-random and coverage-driven methodologies, as well as protocol-level knowledge spanning AMBA bus families, memory interfaces, and high-speed serial standards.

As the ASIC Verification Engineer, you are responsible for driving block-level and SoC-level verification from test plan through RTL freeze, ensuring that every functional, power, and security requirement is exercised before tape-out. You operate within a multidisciplinary hardware organization, collaborating daily with architecture, design, and DFT teams while owning the verification infrastructure that the full program depends on to ship.

Career Impact: Owning RTL freeze decisions on multi-million-gate SoC programs builds a verification track record that is directly legible to semiconductor hiring managers evaluating senior and lead candidates.

Business Impact: A missed functional bug at tape-out can cost millions in respin fees and months of program delay; your coverage closure work is the mechanism that prevents that outcome for every chip you verify.

Growth Opportunity: Exposure to mixed-signal verification, formal methods, and security-feature negative testing expands your methodology portfolio into areas where verified engineers command a significant market premium.

• Develop test plans for IP, subsystem, and SoC-level verification, covering functional, power-intent, and security scenarios.
• Build and maintain constrained-random UVM testbenches including monitors, checkers, scoreboards, and functional coverage groups.
• Drive verification completion milestones and own RTL freeze decisions in coordination with design and architecture teams.
• Analyze simulation results to identify coverage gaps and implement corrective changes to test methodology.
• Verify bus fabric connectivity and structural integrity at SoC level, including clock-domain crossing and lint checks.
• Validate power-up and power-down sequences against UPF/CPF intent across defined power domains.
• Guide DFT teams on DFT validation flows and validate that design-for-test logic meets specification.
• Mentor junior verification engineers on testbench methodology, scripting practices, and coverage closure strategies.

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent work experience.
• 3 or more years of ASIC verification experience, with hands-on ownership of testbench development and coverage closure.
• Proficiency in SystemVerilog and UVM, including constraint-random stimulus, functional coverage groups, and SVA-based checking.
• Experience verifying AMBA bus protocols (AXI, AHB, APB) and at least one high-speed interface standard such as DDR/LPDDR, PCIe, or USB.
• Demonstrated ability to write simulation control and coverage-collection scripts in at least one scripting language.
• Ability to work independently within a multidisciplinary hardware team spanning architecture, design, and software functions.

• Experience with mixed-signal verification, including behavioral models for analog blocks and AMS testbench development.
• Familiarity with formal verification methods introduced alongside simulation-based flows for control-intensive units.
• Prior work on security-feature verification, including negative testing and RISC-V CPU peripheral logic.
• Exposure to post-silicon lab bring-up and simulation vector porting during chip validation.

• Functional coverage closure rate (%), measured at block, subsystem, and SoC regression checkpoints.
• RTL freeze date adherence, tracking whether verification sign-off is achieved within the committed program schedule.
• Escape rate (count of post-silicon bugs traceable to pre-silicon verification gaps), the primary quality measure for this role.
• Testbench reuse ratio across IP and subsystem levels, reflecting efficiency of the verification infrastructure built.
• DFT validation sign-off cycle count, measuring how many iteration loops are required before DFT integration is accepted.
• Typical tools: simulation (commonly VCS or Xcelium); coverage and debug (commonly Verdi or DVE); scripting (commonly Python or Perl).

• Base Salary Range: $130,000 to $185,000 per year, depending on seniority and location
• Bonus: Annual performance bonus, typically 8% to 15% of base salary
• Equity: RSU grants common at mid-to-large semiconductor companies; vesting over 4 years
• Health Benefits: Medical, dental, and vision coverage; employer typically covers the majority of premiums
• PTO: 15 to 20 days annually, plus paid holidays and sick leave
• Common Perks: Relocation assistance, professional development budget, on-site lab access, employee stock purchase plan

Figures are estimates based on general US market benchmarks and may be outdated. Adjust based on location, company size, and seniority level.

Employment is contingent on successful completion of a background check, and all applicants must be authorized to work in the United States without sponsorship unless otherwise specified. All qualified individuals are considered for employment without regard to race, color, religion, sex, national origin, age, disability, veteran status, or any other characteristic protected under applicable federal, state, or local law. Reasonable accommodations for applicants with disabilities are available upon request throughout the hiring process.

The ASIC Verification Engineer owns the delivery of a bug-free complex SOC by leading verification completion, driving RTL freeze decisions, and building test benches with monitors, checkers, and scoreboards, working closely with architecture, systems, and design teams. This work directly supports pre-silicon quality across IP, subsystem, and SOC levels, enabling reliable chip delivery and reducing post-silicon risk.

Key Responsibilities

• Lead an SOC design verification team and own the delivery of a bug-free complex SOC by working closely with architecture, systems, and design teams.
• Develop pre-silicon verification tests to verify that systems meet design requirements.
• Build test benches with monitors, checkers, scoreboards, and other components as necessary.
• Create test plans for RTL validation, define and run system simulation models, and find and implement corrective measures for failing RTL tests.
• Analyze results and use them to modify testing methodology.
• Drive verification completion and RTL freeze decisions.
• Contribute to test plans and test infrastructure development.
• Own and drive block-level verification.
• Write scripts for automating verification and collecting coverage results.
• Provide IP, subsystem, and SOC validation consultations.
• Guide DFT teams on DFT validation.

Required Qualifications

• 4–8 years of working experience in a related field, or 8–15 years for senior or lead level.
• Experience in simulation and debug of RTL, PA-RTL, GLS, and PA-GLS.
• Expertise in test planning and creating direct tests, including planning test scenarios and implementing tests using SV, UVM, SVA, OVM, eRM, and C-based verification methodologies.
• Experience in constrained random and coverage-driven verification methodologies.
• Experience in mixed-signal verification, including developing AMS test benches and behavioural models for analog blocks.
• Experience with UPF/CPF, including verification of power intent and power-up/down sequences.
• Proficiency in logic verification, processor-based verification, and AMS verification.
• Proficiency in test architecture and test environment development, including building test benches and implementing monitors, checkers, and scoreboards.
• Architecture and verification knowledge of bus protocols, including AXI, AHB, APB, and OCP, as well as protocols such as DDR/LPDDR, PCIe, USB, and Ethernet.
• Understanding of PHYs, including SERDES PHY and DDR/LPDDR PHYs.
• Proficiency in Verilog, SystemVerilog, VHDL, C, SystemC, and SV-UVM.
• Experience with simulators such as VCS, NC-Verilog, Xcelium, and ModelSim.
• Proficiency in scripting languages such as Perl, Python, and Shell/Tcl.

Embedded within multi-disciplinary design groups, the ASIC Verification Engineer leads microarchitecture of the test bench and delivers verification across high-performance, low-power on-chip fabric, interconnect, and fabric components at both SoC and sub-system levels. Working closely with design and systems teams, this role ensures methodology, flows, and structural checks are maintained through chip fabrication and lab porting.

Core Functions

• Lead microarchitecture of the test bench.
• Verification of high-performance, low-power on-chip fabric, interconnect, and fabric components.
• Analyze and configure the verification test bench at SoC level and sub-system level, including instantiation, connectivity, and structural checks such as Lint and CDC.
• Develop and maintain methodology, flows, and checks for designs.
• Work with multi-disciplinary groups to deliver verification tests.
• Port tests in the lab after chip fabrication.

Qualifications & Experience

• Bachelor's or Master's degree in Electrical Engineering or Computer Science with 5–15 years of experience.
• Experience in design and verification of multi-million-gate ASICs using Verilog or SystemVerilog.
• Hands-on experience across all aspects of the ASIC development process with proficiency in ASIC verification.
• Experience in writing test benches, test plans, and test vector specifications.
• Experience with multiple clock domains and asynchronous interfaces.
• Experience or knowledge of system architecture, CPU and IP integration, and power and clock domains.
• Knowledge of SoC system bus, fabric, and interconnect design verification.
• Knowledge of memory controller design verification and IP/sub-system-level verification.
• Expertise in SystemVerilog and high-level languages such as C and C++.
• Familiarity with computer architecture concepts, software concepts, and operating systems concepts.
• Familiarity with scripting languages such as Perl and Python.

Reporting to the verification lead, the ASIC Verification Engineer shapes the delivery of the security engine by performing IP-level and engine-level verification for RISC-V CPU peripheral logic and security feature-related IP using UVM and formal verification methods. Partnering with multi-disciplinary engineering teams, this role strengthens pre-silicon security assurance through negative testing and sophisticated test bench development.

Primary Duties

• Verifies and delivers the security engine, including IP-level verification for RISC-V CPU peripheral logic.
• Security feature-related IP.
• Performs engine-level verification across multiple smaller IPs using UVM at the unit level.
• Applies formal verification methods for recent and future verification work.
• Conducts negative testing for security-related features.

Skills & Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of experience with a Master's degree, or 5+ years with a Bachelor's degree.
• Experience with verification methodology, tools, and flow.
• Experience with verification behaviour models using C, C++, or SystemC.
• Experience with sophisticated test bench setup, including SVA, functional coverage groups, and random constraints.
• Programming skills in SystemVerilog, Perl, and C/C++.
• Proficiency in scripting using Perl, Python, or shell.
• Knowledge of makefiles and tree infrastructure.
• Ability to work independently and within a multi-disciplinary team environment.