ASIC PHYSICAL DESIGN ENGINEER JOB DESCRIPTION

Tapeout deadlines in advanced technology nodes are unforgiving: a missed signoff check at 5nm or 7nm can delay product launch by quarters and cost millions in re-spin. ASIC Physical Design Engineers own the implementation path that keeps those deadlines intact, translating verified RTL into production-ready GDSII across the full chain of synthesis, place-and-route, timing closure, and physical verification. The role sits at the center of silicon development, accountable to both RTL designers upstream and EDA tool ecosystems downstream. FinFET process constraints and the growing complexity of coherent optical and high-speed networking ASICs make the technical bar for this function unusually high.

As the ASIC Physical Design Engineer, you are accountable for delivering tapeout-quality implementation across advanced process nodes, owning every stage from floorplanning through DRC/LVS signoff, and driving the power, performance, and area decisions that define chip viability. You work within a multidisciplinary silicon team spanning RTL design, analog integration, and EDA vendor management, with scope that expands to technical leadership of senior engineers as the program scales.

Career Impact: Repeated tapeout execution at 7nm and below is among the most credentialing track records an IC engineer can build, directly shaping your market value across fabless semiconductor, hyperscaler silicon, and telecom ASIC hiring pools.

Business Impact: The physical implementation decisions you make- power grid architecture, clock tree strategy, signoff corner selection- determine whether a next-generation coherent optical or networking ASIC ships on schedule or returns for a costly re-spin.

Growth Opportunity: Ownership of advanced-node flows and cross-functional EDA vendor engagement positions engineers in this role for principal- or staff-level IC design leadership, with a clear path toward chip architect or engineering director titles as program complexity increases.

• Lead physical implementation of complex ASICs from synthesis through GDSII, covering floorplanning, place-and-route, and clock tree synthesis.
• Drive timing closure across multiple process corners, resolving setup, hold, and signal integrity violations in advanced technology nodes.
• Deliver signoff verification including DRC, LVS, formal equivalence check, IR drop, and electromigration analysis to tapeout quality.
• Collaborate with RTL designers to debug physical implementation issues and evaluate architectural tradeoffs affecting power, performance, and area.
• Develop and maintain physical design flows, automation scripts, and methodologies to improve implementation efficiency and repeatability.
• Evaluate EDA vendor tools, process node IP, and design collateral, providing technical recommendations to the engineering team.
• Manage cross-functional stakeholders across analog, digital, and verification teams throughout the chip development program.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent work experience.
• 7 or more years of ASIC physical design experience, with demonstrated tapeout ownership at advanced technology nodes.
• Proficiency in the full physical design flow including synthesis, place-and-route, STA, CTS, power analysis, and formal verification.
• Hands-on experience with FinFET process nodes at 7nm or below, including an understanding of associated DRC and timing constraints.
• Experience integrating mixed-signal IP including embedded memories, I/O cells, and analog macros into physical implementation.
• Strong scripting ability to develop and maintain automation for physical design flows and data extraction.
• Solid analytical and communication skills, with the ability to present technical tradeoffs clearly to engineering and program stakeholders.

• Master's degree in Electrical Engineering or Computer Engineering with a focus on VLSI or IC design.
• Prior experience in telecom, coherent optical, or high-speed networking ASIC programs where signal integrity and power constraints are critical.
• Background in IP evaluation and process node selection, including participation in vendor technical reviews.
• Demonstrated experience mentoring engineers and providing technical leadership within a physical design team.

• Tapeout schedule adherence, measured against committed milestone dates across all signoff checks.
• Power, performance, and area closure rate, tracking how often implementation meets defined PPA targets without re-spin.
• DRC/LVS clean percentage at first physical verification run, reflecting flow quality and upstream collaboration rigor.
• Timing violation count at signoff, measuring effectiveness of closure methodology across all corners and modes.
• Script automation coverage, tracking the share of recurring implementation steps covered by maintained flow scripts.
• Typical tools: place-and-route EDA (commonly Cadence Innovus or Synopsys IC Compiler); signoff and verification (commonly Synopsys PrimeTime, Calibre, or Conformal).

• Base Salary Range: $155,000 to $220,000 annually, depending on node experience and tapeout history
• Bonus: Annual performance bonus, typically 10 to 20% of base salary
• Equity: RSU grants common at mid-to-large semiconductor firms; options typical at early-stage companies
• Health Benefits: Medical, dental, and vision coverage; employer contribution varies by company size
• PTO: 15 to 20 days annually, plus federal holidays and discretionary sick leave
• Common Perks: Relocation assistance, professional development budget, conference attendance, patent incentive programs

Figures are estimates based on general US market benchmarks and may be outdated. Adjust based on location, company size, and seniority level.

Employment eligibility verification and a successful background check are conditions of hire for all positions. All qualified applicants will be considered without regard to race, color, religion, sex, national origin, disability, veteran status, age, sexual orientation, gender identity, or any other characteristic protected under applicable federal, state, or local law. Reasonable accommodations for qualified individuals with disabilities are available upon request throughout the application and employment process. Candidates must be authorized to work in the United States.

The ASIC Physical Design Engineer owns block-level physical implementation across synthesis, floor planning, place and route, timing closure, and formal verification in advanced technology nodes, partnering with logic designers to drive architectural feasibility studies and RTL tradeoffs. Working alongside hardware teams to evaluate vendors, process nodes, and IP, the role shapes physical design methodologies and automation scripts that enable successful design closure.

Key Responsibilities

• Perform block-level physical implementation steps, including synthesis, floor planning, place and route, power and clock distribution, congestion analysis, timing closure, CDC analysis, and formal verification.
• Work with logic designers to drive architectural feasibility studies and develop timing, power, and area design goals.
• Explore RTL and design tradeoffs for physical design closure.
• Perform technical evaluations of vendors, process nodes, and IP, and provide recommendations.
• Develop physical design methodologies and automation scripts for various implementation steps.

Required Qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 2 years of experience in ASIC physical design flows and methodologies in advanced nodes.
• Experience in synthesis, place and route, STA, formal verification, CDC, and power analysis.
• Experience leading one or more aspects of physical design.
• Experience in IP integration, including memories, I/Os, and analog IP.
• Experience solving physical design challenges across various technologies, including embedded processors, double data rate, and networking fabrics.
• Experience in extraction of design parameters, quality of results, and analyzing trends.
• Knowledge of Verilog/System Verilog, semiconductor device physics, and transistor characteristics.
• Experience using tools such as Design Compiler, Innovus/EDI, and Conformal, and in scripting languages such as Python, Tcl, or Perl.

Embedded within a team-oriented IC development environment, the ASIC Physical Design Engineer develops well-documented, power-efficient RTL and designs integrated memory and storage SoC subsystems across logic synthesis and static timing analysis. Working closely with backend, layout, architecture, and verification teams, the role delivers chip-level floor planning, clock tree synthesis, and post-layout timing analysis that advance complex digital IC projects from specification to verified silicon.

Core Functions

• Set up and maintain the design environment and process.
• Generate well-documented, power-efficient, and synthesis-friendly RTL.
• Write comprehensive verification and test plans for blocks under ownership.
• Develop and design integrated memory and storage SoC subsystems.
• Work on logic synthesis and static timing analysis.
• Work with backend and layout engineers on chip-level floor planning, power planning, macro.
• Standard cell placement, clock tree synthesis, design rule checks, and post-layout timing analysis.

Qualifications & Experience

• BSEE, BSCS, or BSCE degree with 7–10 years of related experience.
• MSEE, MSCS, or MSCE degree with 5–8 years of related experience.
• Proven track record of collaborating with architecture and verification teams to design, code, and verify PCIe controllers, memory controllers, flash controllers, embedded processors, high-performance IPs, and/or SoC designs.
• Strong experience with PCIe interface design, coding, and verification at the module level, and with integrated microcontroller subsystems.
• Skilled at debugging, fixing, and validating pre- and post-silicon IP and sub-system logic issues and bugs.
• Excellent knowledge of RTL design, verification, and timing closure.
• Strong understanding of SoC design challenges.
• Demonstrated ability to innovate and make architectural and design trade-offs to balance performance, power, and area.
• Familiar with design environments, process flows, tool suites, methodologies, and optimization methods.
• Proficiency in programming and scripting languages, including C/C++, Perl, and Unix/Linux.

Reporting to engineering leadership, the Lead ASIC Physical Design Engineer leads planning, scheduling, and day-to-day execution across all phases of the silicon product life cycle, managing milestones, budgets, and technical risks for mixed-signal ASIC development programs. Partnering with hardware engineering teams, leads, and external vendors, the role builds cross-functional project plans and stakeholder communications that deliver outstanding program outcomes on a realistic schedule.

Primary Duties

• Organize and drive planning, scheduling, and day-to-day execution to support the silicon design team.
• Collaborate with leads and engineering teams to estimate and prioritize tasks, maintaining high quality on a realistic delivery schedule.
• Develop and lead project plans covering scope, schedule, and budget to ensure alignment with key partners and business needs.
• Manage project schedules and quality, identify possible issues and risks, and communicate them clearly to project stakeholders.
• Facilitate recurring project meetings and operational checkpoint activities throughout the project life cycle.
• Set clear and targeted communications to management on project information, including project plan, key dates, and project status.
• Provide hands-on project management, cross-functional coordination, and internal and external team communications to deliver outstanding program outcomes.
• Take responsibility for release schedules and milestones, maintaining high velocity in a fast-paced environment.
• Engage with vendors and customers in external program management activities.

Skills & Qualifications

• Bachelor's degree in a technical field.
• 5+ years of experience in semiconductor technologies with participation in multiple tapeouts.
• Experience in project management in mixed-signal ASIC development, including setting up project management initiatives from scratch in a startup or new business unit environment.
• Experience with standard CAD tools and scripting environments, including Python and TCL.
• Experience influencing decisions and leading teams in a matrix environment.
• Expert user of program management tools such as MS Project, Asana, Smartsheet, or similar.
• Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields.
• Excellent communication and technical presentation skills.
• Ability to react to change and thrive in a fast-paced environment, with strong attention to detail and the ability to multitask.

Sitting at the intersection of advanced physical design and next-generation telecom systems, the ASIC Physical Design Engineer delivers highly complex ASIC implementation activities spanning power analysis, floorplanning, place and route, timing closure, and full DRC/LVS signoff across major EDA tool suites for 100G-1T coherent optical communications products. Operating across analog and digital teams while interfacing with EDA vendors, the role ensures tape-out quality at advanced technology nodes that underpin next-generation telecom infrastructure.

Duties

• Deliver physical design implementation activities, including power analysis, electromigration, IR signoff, process corner decisions, floor planning and partitioning, synthesis, place and route, STA, formal equivalence check, clock tree synthesis, timing closure, signal integrity, power grid analysis, and physical verification DRC/LVS, across all major EDA tool suites.
• Work closely with RTL designers to debug and root-cause physical implementation issues related to design and tools.
• Arrive at feasible solutions through the augmentation of input and design collateral.
• Deliver design flows for place and route, STA, formal equivalency, power grid analysis, and physical verification DRC/LVS across the design space.
• Manage stakeholders across analog and digital teams while interfacing with EDA vendors on issues, features, and enhancements.

Requirements

• Bachelor's degree in electronic engineering or equivalent qualification in training and experience.
• At least 8 years of professional engineering experience, including experience in advanced technology nodes at 5nm and below.
• Successful execution of ASICs from product definition to production release, with FinFET expertise.
• Prior experience in the telecom design space.
• Familiar with industry-standard CAD methodologies from Cadence, Synopsys, and/or Mentor.
• Good scripting skills in Perl and TCL.
• Experience with digital signal processing algorithms is a plus.
• Solid analytical, written, and verbal communication and presentation skills.
• Self-motivated with the ability to work independently without supervision.

A key member of the physical design organization, the ASIC Physical Design Engineer leads a team of five to eight senior engineers as technical lead, driving physical verification and sign-off for complex chips at advanced technology nodes from RTL to GDSII. Collaborating across multi-site engineering and management teams, the role builds hands-on flow development and scripting capabilities that enable the team to identify, break down, and resolve complex technical problems at 7nm and below.

Functions

• Lead a team of five to eight senior-level engineers as technical lead.
• Drive physical verification and signoff for complex chips at advanced technology nodes.
• Identify complex technical problems, break them down, summarize possible solutions, and lead the team in the right direction.
• Develop and maintain hands-on flow development and scripting for physical verification.
• Schedule discussions and drive execution with multi-site engineers and managers.

Experience & Qualifications

• MSEE or MSCE with over 6 years of experience in ASIC physical design from RTL to GDSII.
• Hands-on experience taping out at advanced technology nodes at 7nm and below.
• Strong physical verification skills with an in-depth understanding of challenges and rules in advanced technology nodes at 7nm and below.
• In-depth understanding of all aspects of the physical design flow from synthesis to signoff.
• Working experience with CAD tools from Synopsys, Cadence, and Mentor Graphics.
• Ability to provide mentorship and guidance to junior and senior engineers and to function as an effective team player.
• Strong analytical and problem-solving skills with attention to detail.
• Strong communication, time management, and presentation skills.
• Must be a self-starter with the ability to independently and efficiently drive tasks to completion.