ASIC ENGINEER JOB DESCRIPTION

An ASIC Engineer owns design and verification work at the register-transfer level, within chip development programs that may span hundreds of millions of gates and multiple tape-out milestones. Silicon does not revise itself. When RTL is poorly specified, or validation plans miss corner cases, functional ECO cycles eat schedule and drive up NRE cost on fabrication runs that cannot be undone. This role answers that problem directly, operating across front-end design, functional coverage closure, and post-silicon characterization within SoC development teams.

As the ASIC Engineer, you will own RTL implementation, verification planning, and lab-based silicon validation for one or more functional blocks within a complex SoC program, ensuring design intent survives synthesis through to silicon bring-up. You will collaborate daily with chip architects, physical design engineers, and firmware teams, typically reporting to a principal engineer or engineering manager overseeing a specific functional domain.

Career Impact: Deep ownership of RTL-to-silicon delivery on commercial SoC programs builds a verified track record in a discipline where hands-on tape-out experience is a hard filter at every senior level.

Business Impact: Functional bugs caught in pre-silicon simulation cost a fraction of those found after fabrication; your verification closure work directly determines the cost and schedule of a product reaching production.

Growth Opportunity: Experience spanning RTL design, UVM-based verification, and post-silicon characterization positions you for Principal Engineer or Physical Design Lead roles as chip complexity and AI-accelerator demand continue to expand the market.

• Author RTL design specifications and participate in micro-architecture reviews to define functional block behavior.
• Implement Verilog or SystemVerilog RTL to meet timing, performance, and power targets.
• Develop UVM-based verification environments and define validation plans for assigned functional features.
• Collaborate with physical design engineers to resolve timing closure, DRC, and place-and-route violations.
• Execute post-silicon validation and characterization tests in the lab, including debug of bring-up failures.
• Triage and root-cause simulation failures, software bring-up issues, and field-reported defects.
• Support design methodology improvements and contribute to flow scripts to reduce closure cycle time.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent work experience.
• 3 or more years of ASIC design or verification experience, with demonstrated ownership of RTL blocks through tape-out or post-silicon validation.
• Proficiency in RTL design using Verilog or SystemVerilog, including waveform and interactive debug.
• Hands-on experience developing functional coverage models and closing code coverage gaps with a verification team.
• Ability to read and interpret physical design feedback including timing reports, IR-drop analysis, and DRC/LVS results.
• Familiarity with standard electrical lab equipment such as oscilloscopes, logic analyzers, and pattern generators for silicon bring-up.
• Scripting capability in at least one language to automate design flow or data analysis tasks.

• Master's degree in Electrical Engineering with a focus on VLSI design or digital systems.
• Experience with UVM methodology, including environment architecture and coverage-driven verification planning.
• Background in post-silicon characterization of communication or memory interface IP, including protocol-level debug.
• Familiarity with hierarchical floor planning, clock planning, or chip-level integration tasks in a physical design flow.

• RTL freeze milestone adherence, measured against block-level tape-out schedule commitments.
• Functional coverage closure rate, tracking percentage of defined coverage points hit at sim sign-off.
• DRC/LVS clean-out cycle count, reflecting efficiency of physical design feedback turnaround.
• Post-silicon bring-up defect rate per block, measuring validation plan completeness before first silicon.
• ECO count attributed to design specification gaps, indicating upstream specification quality.
• Typical tools: HDL simulators (commonly VCS or ModelSim); EDA P&R platforms (commonly Synopsys ICC2 or Cadence Innovus).

• Base Salary Range: $110,000–$160,000 depending on seniority and location
• Bonus: 5–15% annual performance bonus
• Equity: RSUs or stock options common at mid-to-large semiconductor firms
• Health Benefits: Medical, dental, and vision; employer-subsidized premiums standard
• PTO: 15–20 days annually plus company holidays
• Common Perks: Relocation assistance, conference attendance, continued education reimbursement

Figures are estimates based on general US market benchmarks and may be outdated. Adjust based on location, company size, and seniority level.

Background screening, including verification of employment history and education, is a standard condition of hire. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, age, disability, veteran status, sexual orientation, gender identity, or any other characteristic protected under applicable federal, state, or local law. Candidates requiring a reasonable accommodation to participate in the hiring process should notify the recruiting team at any stage. Applicants must be authorized to work in the United States.

The ASIC Engineer owns full-cycle development of SoC hardware assist functions, covering architecture design, logic design, synthesis, and timing analysis from specification through silicon characterization. Working within a hardware engineering team and interfacing with design and test workflows, this role delivers verified, documented silicon that enables reliable image processing, motor control, and communication functionality in production devices.

Key Responsibilities

• Develop, design, verify, and document ASIC development.
• Determine architecture design, logic design, and system simulation.
• Analyse all aspects from high-level design to synthesis, place and route, and timing and power utilization.
• Design image processing, motor control, processor and memory interface, communication, and other hardware assist functions for SoC ASICs.
• Verify image processing, motor control, processor and memory interface, communication, and other hardware assist functions for SoC ASICs using UVM and C/C++-based function modeling and scripting.
• Document hardware assist functions for both design and test specifications, including analysis and characterization of fabricated silicon upon design completion.
• Implement low-level firmware to interface with and test ASIC/FPGA/CPLD hardware assist.
• Use electrical laboratory equipment to establish operational data, conduct experimental tests, and evaluate results.

Required Qualifications

• Bachelor's degree or higher in Electrical Engineering.
• 0–3 years of experience in the industry.
• Familiarity with UVM, VLSI design, ARM, RISC-V, and ASIC/FPGA design.
• Proficiency in VHDL, Verilog, SystemVerilog, C/C++, LabVIEW, Perl, and Python.
• Experience with Synopsys and Mentor Graphics EDA tools.
• Familiarity with typical electrical laboratory equipment, including digital oscilloscopes, logic analyzers, and pattern generators.
• Understanding of computer hardware, file servers, networks, and database management.

Embedded within the chip physical design team, the ASIC Engineer leads all phases of physical design implementation for large, complex, high-performance ASICs, encompassing hierarchical floorplanning, place and route, and chip-level clock planning. Working closely with chip architects, front-end design engineers, package engineers, and block physical design engineers, this role shapes an optimal chip floorplan that meets schedule, timing, EM, IR drop, DRC, and LVS requirements.

Core Functions

• Lead all phases of physical design implementation for large, complex, high-performance ASICs.
• Perform hierarchical multi-level full-chip floor planning, bus routing planning, sequential pipeline planning, and chip-level clock planning.
• Collaborate with chip architects, front-end design engineers, package engineers, and block physical design engineers to develop an optimal chip floorplan.
• Perform detailed top-level place and route to meet project goals in terms of schedule, timing, EM, IR drop, DRC, and LVS.
• Run physical design verification flow at chip level.
• Provide feedback and guidelines to block-level physical design engineers to resolve DRC/LVS violations.
• Develop and modify design flow as needed to meet overall design QOR and chip integration requirements.

Qualifications & Experience

• Master's degree in Electrical Engineering with 10+ years of physical design experience.
• 3+ years in a leadership role.
• Deep understanding of all aspects of physical design, including place and route, DRC/LVS, IR drop, timing, and functional ECO.
• Hands-on experience with Synopsys ICC2 and Cadence Innovus P&R CAD tools and flows.
• Ability to write TCL, Perl, and shell scripts to resolve design closure problems.
• Strong interpersonal and team collaboration skills.

Reporting to the manager of overall ASIC/FPGA validation, the ASIC Engineer leads ownership of validation environment development and characterization of specified functional features, including defining the validation plan for a subset of features and participating in full-chip validation efforts. Partnering with cross-functional teams during system-level debug and process improvement, this role delivers technical quality and timely completion that strengthens the reliability of ASIC/FPGA designs through structured validation methodology.

Primary Duties

• Take full ownership of validation environment development and/or validation and characterization of specified functional features.
• Participate in specification of validation environment.
• Component selection required to carry out validation.
• Define and own the validation plan for a subset of features.
• Participate in system-level debug to isolate issues related to ASIC/FPGA.
• Participate in full-chip validation and characterization efforts.
• Participate in process and checklist definition and improvements.
• Mentor team members.

Skills & Qualifications

• 1+ years of experience with a Master's degree.
• 4+ years with a Bachelor's degree.
• Experience with post-silicon validation.
• Proficiency in scripting languages, preferably Python.
• Basic RTL design and verification skills, with proficiency in Ethernet and/or OTN protocol standards.
• Ability to review architecture, requirements, and micro-architecture details.
• Ability to contribute to improving validation methodology and exploring new methodologies to improve quality and reduce pain points in project execution.
• Strong communication and interpersonal skills.

Sitting at the intersection of RTL design and physical implementation, the ASIC Engineer delivers Verilog RTL that meets timing and performance requirements while authoring design specifications and collaborating with verification and physical design teams to close coverage and place-and-route issues. Operating across simulation, lab-based post-silicon validation, and customer failure triage, this role builds reliable silicon by bridging design methodology development with hands-on diagnostic testing.

Duties

• Author design specifications and participate in micro-architecture specification reviews.
• Implement Verilog RTL to meet timing and performance requirements.
• Help define, evolve, and support design methodology.
• Develop and analyse functional coverage.
• Collaborate with the verification team to address design bugs and close code coverage.
• Work closely with the physical design team to close timing and place-and-route issues.
• Triage, debug, and root-cause simulation, software bring-up, and customer failures.
• Perform diagnostic and post-silicon validation tests in the lab.

Requirements

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• 5+ years of ASIC design experience with a Bachelor's degree.
• Excellent Verilog/SystemVerilog programming skills.
• Strong interactive and waveform debug skills.
• Scripting experience in Python, Perl, TCL, or shell programming is highly desirable.
• Strong written and verbal communication skills.
• Collaborative and team-focused, with a commitment to learning and growth.