ASIC DIGITAL DESIGN ENGINEER JOB DESCRIPTION

Semiconductor IP development demands absolute precision: a verification gap in a PCIe or USB interface block can survive simulation, reach silicon, and cost millions in a respin. An ASIC Digital Design Engineer owns the RTL-to-closure pipeline, translating architecture specifications into verified, synthesizable logic that meets timing, power, and functional coverage targets. Few engineering seats carry this combination of depth and consequence. Deep sub-micron design rules, SoC-level integration constraints, and protocol compliance regimes like AMBA and Ethernet frame every decision this role makes.

As the ASIC Digital Design Engineer, you will own the full RTL design and verification lifecycle for digital and mixed-signal IP blocks, delivering silicon-ready logic against published functional coverage and timing closure metrics. You operate within a verification and implementation team, contributing independently on complex subsystem assignments while coordinating with architects and senior engineers on cross-block integration and customer bring-up activities.

Career Impact: Deep ownership of PCIe, USB, and AMBA protocol verification at the IP level builds the kind of silicon-proven expertise that commands premium standing across fabless and semiconductor IP firms.

Business Impact: Verification closure decisions you make directly determine whether IP blocks reach tape-out on schedule or require costly respin cycles affecting downstream SoC customers.

Growth Opportunity: Senior engineers who master UVM-based verification environments and cross-domain analog co-simulation are well-positioned to advance into Verification Lead or Design Architect roles within semiconductor IP organizations.

• Define verification architecture, test plans, and functional coverage strategies for digital IP blocks targeting PCIe, USB, AMBA, and Ethernet protocols.
• Develop UVM-based testbench environments and implement constrained-random test cases to achieve RTL, gate-level, and co-simulation coverage closure.
• Implement RTL logic and subsystem integrations, including DFT insertion and constraint development, against published architecture specifications.
• Evaluate synthesis, timing analysis, and power analysis outputs to ensure design meets deep sub-micron implementation targets.
• Debug simulation failures across RTL, GLS, and mixed-signal co-simulation environments to root-cause functional and coverage gaps.
• Review technical documentation including verification plans, architecture documents, and coverage reports, providing feedback that improves team output quality.
• Support customer bring-up of IP blocks within third-party simulation environments, resolving integration issues against protocol specifications.
• Guide junior engineers on test case development, assertion planning, and verification methodology to maintain team delivery cadence.

• Bachelor's degree in Electrical Engineering, Electronics Engineering, or Computer Engineering, or equivalent work experience.
• 8 or more years of ASIC digital design and verification experience, with hands-on ownership of functional and code coverage closure.
• Demonstrated expertise in SystemVerilog and UVM-based verification methodology, including testbench architecture and functional coverage model development.
• Solid understanding of one or more high-speed connectivity protocols, including PCIe, USB, AMBA, or Ethernet, with experience verifying against published specifications.
• Proficiency in RTL design using Verilog or VHDL, with working knowledge of synthesis and static timing analysis flows.
• Experience with scripting languages for verification automation and design flow tasks, including Perl, Python, Tcl, or Shell.
• Demonstrated ability to produce clear technical documentation including verification plans, architecture notes, and test reports.
• Strong analytical and debug skills, with a track record of resolving simulation failures through data-driven root-cause analysis.

• Experience with analog-digital co-simulation and mixed-signal verification using behavioral SV models or real-number modeling techniques.
• Familiarity with DFT architecture, including scan insertion and ATPG flows, within deep sub-micron CMOS design environments.
• Exposure to FPGA-based prototyping workflows used for pre-silicon software and hardware validation.
• Prior involvement in IP bring-up or customer integration support within a fabless or semiconductor IP licensing business model.

• Functional coverage closure rate, measuring the percentage of planned coverage points hit before sign-off.
• Code coverage percentage across RTL and gate-level simulation runs, tracked against team closure targets.
• Simulation regression pass rate, reflecting testbench stability and test case completeness over a verification cycle.
• Defect escape rate post-tape-out, measuring verification thoroughness against silicon-revealed bugs.
• Review cycle count per architecture or verification document, reflecting documentation clarity and first-pass quality.
• Typical tools: HDL simulators (commonly VCS or Xcelium); coverage and formal verification tools (commonly Verdi or JasperGold); scripting environments (Python, Perl, Tcl).

• Base Salary Range: $140,000 to $185,000 annually, depending on seniority and location
• Bonus: Annual performance bonus, typically 10% to 15% of base salary
• Equity: RSUs common at established semiconductor firms; options more typical at early-stage IP companies
• Health Benefits: Medical, dental, and vision coverage; employer contribution toward premiums standard
• PTO: 15 to 20 days annually, plus standard US public holidays
• Common Perks: Relocation assistance, conference and training budget, on-site engineering resources

Figures are estimates based on general US market benchmarks and may be outdated. Adjust based on location, company size, and seniority level.

Employment decisions are made without regard to race, color, religion, sex, national origin, age, disability, genetic information, veteran status, sexual orientation, gender identity, or any other characteristic protected under applicable federal, state, or local law. Candidates requiring reasonable accommodations during the application or interview process are encouraged to make that need known. Final employment offers are contingent on satisfactory completion of a background check. Applicants must be authorized to work in the United States.

The ASIC Digital Design Engineer owns the full verification lifecycle, from architecting verification environments and test benches to developing closure metrics that include functional coverage and code coverage. Embedded in an engineering team, this role shapes design quality by guiding engineers on test case development and resolving complex issues through creative, effective problem-solving.

Key Responsibilities

• Resolve complex issues in creative and effective ways.
• Define various aspects of the verification flow.
• Create architecture documents for the verification environment, test bench, and test cases.
• Create verification closure metrics, including checks, assertions, functional coverage, and code coverage.
• Develop the verification environment.
• Guide engineers to write test cases for functional verification and code coverage.

Required Qualifications

• Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering.
• At least 9 years of related experience.
• Hands-on experience in digital and mixed-signal design verification processes.
• Experience in HVL-based test environments and test plan development.
• Understanding of one or more connectivity protocols, including USB, PCI Express, Ethernet, and AMBA.
• Expertise in verification methodologies, including UVM, VMM, and OVM.
• In-depth understanding of one or more industry-standard simulators.
• Familiarity with scripting languages, including Verilog, Perl, and Python.
• Demonstrates good data-backed debug and problem-solving skills.

Embedded within a semiconductor engineering team, the ASIC Digital Design Engineer contributes to the development and validation of complex digital mixed-signal designs for high-speed interface IP. Working closely with more experienced personnel, this role builds productive working relationships while assembling subsystem RTL, preparing technical reports, and advancing design quality through disciplined verification activities.

Core Functions

• Contribute to the development and validation of complex digital mixed signals for high-speed interface IP.
• Engage in verification activities under the supervision of more experienced personnel and exercise judgment to determine appropriate actions to achieve required specifications.
• Assemble and implement subsystem RTL, constraints, and DFT architecture for internal subsystems.
• Participate in applicable product and project reviews.
• Prepare and present reports outlining the outcome of technical projects.
• Build productive working relationships within the team.

Qualifications & Experience

• University degree in Electronics Engineering or Computer Science.
• At least 2 years of relevant experience.
• Deep knowledge of IC design flows.
• Analog design knowledge and understanding of analog tools and SPICE simulators.
• Experience in Verilog/VHDL and expertise in SystemVerilog, VMM, OVM, or UVM.
• Proficiency in at least one programming language, including Python, C, C++, or MATLAB.
• Exposure to Unix, Perl, and TCL scripting.
• Experience producing high-quality technical documentation.
• Good problem-solving and organisational skills.
• Good English communication skills and ability to work as a team player.

Reporting to engineering leadership, the ASIC Digital Design Engineer leads the definition, development, and verification of semiconductor integrated digital circuits and subsystem integrations, spanning RTL development through verification coverage metrics. Partnering with cross-functional teams, this role delivers rigorous documentation for circuit development and test plans that advance the reliability of FPGA and ASIC design flows.

Primary Duties

• Define, develop, and verify semiconductor integrated digital circuits and subsystem integrations.
• Participate in architecture design exploration, logic design, and verification.
• Implement simulation test cases to verify developed system behaviour.
• Evaluate and exercise various aspects of the development flow, including RTL development, functional simulation, constraint development, design for test logic, synthesis, timing analysis, power analysis, behavioural modelling, and verification coverage metrics.
• Generate documentation for circuit development, test plans, verification environments, and usage.

Skills & Qualifications

• Relevant degree in Electronic Engineering.
• General knowledge base in digital systems and microelectronics.
• Knowledge of Verilog hardware description language and verification methodologies.
• Knowledge of FPGA or ASIC design flows.
• Capable of producing high-quality technical documentation.
• Able to build and maintain productive working relationships inside and outside the team.
• Demonstrates a desire to learn and explore new technologies.
• Solid English communication skills.

Sitting at the intersection of verification engineering and customer-facing IP support, the ASIC Digital Design Engineer leads the development of verification architectures, test plans, and coverage closure across RTL, GLS, and co-simulations. Operating across internal technical reviews and customer simulation environments, this role shapes high-quality IP delivery by driving protocol-level verification using third-party VIP and improving development processes.

Duties

• Develop and review the verification architecture and test plan.
• Develop the verification environment.
• Perform verification using internal or third-party VIP for the protocol of interest.
• Debug simulations, including those of real signals modelled using SystemVerilog for analog.
• Perform RTL, GLS, and co-simulations and drive coverage closure.
• Participate in technical reviews and contribute actively.
• Participate in customer support with bring-up of IP in customer simulation environments.
• Follow and improve the development process to ensure high-quality output.

Requirements

• B.E./B.Tech with 10 years of relevant experience, or M.E./M.Tech with 8 years of relevant experience, in Electronics, Telecommunication, or Computer Engineering.
• Hands-on experience creating verification environments from functional specifications.
• Hands-on experience with HVL or HDL, including VHDL and SystemVerilog.
• Experience in test planning, coverage planning, and assertion planning.
• Knowledge of protocols, including Ethernet, PCIe, and other networking protocols.
• Knowledge of Perl and Shell scripting.
• Good communication, problem-solving, and interpersonal skills, with leadership qualities and the ability to work as a team player.

A key member of a digital design team, the ASIC Digital Design Engineer delivers end-to-end verification coverage by studying interface protocol specifications such as PCIe, USB, DisplayPort, and AMBA, then building verification architectures, test plans, and testbench code from the ground up. Collaborating across engineering and quality assurance functions, this role leads verification reviews that ensure IP cores and SoC designs meet rigorous functional and code coverage standards.

Functions

• Study standard and architecture specifications, including PCIe, USB, DisplayPort, and AMBA.
• Create the verification architecture, test plan, and functional and code coverage plan.
• Perform verification tasks, including testbench and test case coding.
• Define and analyse functional and code coverage.
• Lead verification reviews and quality assurance activities.

Experience & Qualifications

• Deep understanding of digital design and verification, including Verilog, SystemVerilog, and UVM.
• Extensive experience with IP cores or SoC designs for interface protocols, including PCIe, USB, DisplayPort, and AMBA, as well as processors and network chips.
• Knowledge of one or more protocols, including PCIe, USB, AMBA, and DisplayPort.
• Familiarity with C, Shell, Perl, TCL, and Unix environments.
• Ability to communicate in English.