• Provide conformity assessment of pressure equipment to the latest PESR / PED requirements
• Perform detailed assessment under supervision of the manufacturer’s design and arrangements using British, and International Codes & Standards.
• Build strong relationships with key individuals at all levels within the client organisation
• Contribute to relevant standards committees and cross-industry groups
• Identify, pursue and achieve opportunities for commercial growth
• Participate in Verification Plan development.
• Create directed and random Testcases for Functional verification according to Verification Plan.
• Create block-level testbenches and verification components according to UVM.
• Execute and debug Testcases for detailed verification. 
• Communicate with other teams to solve issues.
• Create and maintain auxiliary scripts.
• Meet quality goals for a successful tape-out such as code and functional coverage.

Skills: Conformity Assessment, Design Assessment, Relationship Building, Industry Standards Contribution, Commercial Growth, Verification Plan Development, Testcase Creation, UVM Testbench Development

• Verify analog/digital portions of RF/mm-wave ASICs with sufficiently large test coverage.
• Own top-level schematics for RF, mixed-signal, and digital-signal connectivity.
• Assist in defining chip pin-out and ESD requirements.
• Assist in defining digital architecture, features, and layout to ensure sufficient performance, drive strength, etc.
• Run analog/digital cosims to verify chip-level functionality
• Work with IC designers to define verification methodology to ensure adequate test coverage.
• Ensure ESD compliance, check supply IR drops, run over-voltage and other relevant checks.
• Share/discuss expected chip-level performance with test/product engineers and review relevant measured results against expected/simulated results.
• Join in the development of leading-edge display technologies
• Use advanced verification methodologies for the verification of complex designs
• Provide the documentation and implementation for test benches, DV models, and test cases. 
• Own and execute on the verification of a sizable design by applying UVM verification methodology
• Work with existing tools/flows or develop new tools/flows to complete the assigned verification task.

Skills:  RF/mm-Wave Verification, Schematic Management, Pin-Out Design, Architecture Planning, Co-Simulation Execution, Methodology Development, ESD Compliance, Verification Techniques

• Responsible for verification of block(s) that includes writing tests, assertion and coverage for a block at both unit level and SoC level.
• Understand the Design specifications and develop verification test plan based on feature list
• Create verification environment.
• Create and run tests achieve verification goals.
• Debug failures in simulation to root cause problems.
• Work closely with Design verification team to complete verification.
• Work closely with Design team and participate in specification/ design review meeting and planning.
• Achieve defined code and functional coverage goals.
• Responsbile for the complete verification of the performance and durability of electric motors in Business Unit Hybrid Modules
• Responsible for the complete development and/or verification of a product, given the performance requirements

Skills: Test Script Development, Verification Planning, Environment Creation, Simulation Debugging, Team Collaboration, Design Review Participation, Coverage Analysis, Product Verification

• DC-DC Power solutions evaluation
• Signal quality measurement and analysis of DC/DC power designs
• Signal integrity/Signal integrity failure analysis
• Signal quality measurement and analysis of high speed busses.
• Signal quality measurement and analysis of digital and analog display signals
• Implement improvements in testing, analysis, and simulation techniques
• Guide individual development engineers toward becoming experts in verification, which includes analyzing existing designs and testing methods, developing improved ones, and updating and creating development and testing guidelines for future development
• Work closely with the Design and Testing responsible persons within the group as well as engineers in other departments
• Creation of verification environments, pre-silicon functional verification at the block, chip and system level, reference modeling and post-silicon validation
• Develop environment and test cases to verify hardware security designs

Skills: DC-DC Evaluation, Signal Quality Analysis, Signal Integrity Analysis, Testing Improvement, Mentorship and Training, Cross-Departmental Collaboration, Verification Environment Creation, Hardware Security Testing

• Define the architecture, design and roadmap of the ASIC system
• Design analog and mixed-signal circuits meeting architectural requirements and technical specifications
• Lead ASIC team in design and verification simulations to ensure building blocks meet specifications at the schematic level and at the post-layout extraction stage, while fully provisioning for DFT and DFM
• Collaborate with Layout Engineer to validate proper layout
• Actively participate in the chip bring up, evaluation and characterization
• Collaborate closely with MEMS, Characterization and Test Engineers in the development and characterization of the MEMS-based oscillator
• Document assigned blocks, and hold preliminary and final design review meetings
• Provide technical guidance, coaching, and mentoring of the engineering team while nurturing skill sets and capabilities
• Support other projects as needed by management or as business needs change
• DUT integration and verification for IP delivery sign-off

Skills: ASIC System Architecture, Analog Circuit Design, Design Verification, Layout Validation, Chip Bring-Up, MEMS Collaboration, Technical Documentation, Team Leadership, Project Support, DUT Integration

• Proficient in System VerilogUVMOVM, OOPC++ 
• Knowledge of GPU, experience with Shader, Texture, or Memory System
• Experience with code coverage and functional coverage driven verification methodology. 
• Experience in creating, running and debugging of SystemVerilogUVM constraint-random Testbench. 
• Excellent working knowledge of scripting languages such as Python or Perl.
• Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines. 
• Strong functional verification experience including Test planning, Testbench Architecture, TestCoverage ModelAssertion Development
• Familiar with the logic simulator (Questa/VCS/IUS) and debug tools (Verdi/Visualizer)
• Basic Verilog and C language ability
• Familiar with A MBA protocol
• Experience in script language (TCL, Perl, Python and etc)
• Familiar with SystemVerilog, UVM 
• Familiarity with Bluetooth

Qualifications: BS in Computer Engineering with 4 Years of Experience

• Verification experience in complex IP/SubSystem/SoCs
• Hands on experience using an industry standard verification methodology (UVM/AVM/VMM/eRM).
• Experience writing and debugging SystemVerilog Assertions (SVAs).
• Ability to understand project specifications and come up with a comprehensive set of requirements and develop verification testplan.
• Proven ability to achieve results in a fast moving, dynamic environment.
• Understanding of Microcontroller architectures and products.
• Experience with Object Oriented Programming languages 
• Experience with Python/Perl or other scripting language 
• Experience in a multi-site environment, interacting with teams in other sites.
• Good communication skills.

Qualifications: BS in Computer Science with 6 Years of Experience

• Experience in VLSI design verification
• Experience utilizing UVM and System Verilog
• Understands and develops functional coverage and System Verilog assertions.
• Work experience of a programming and scripting, hardware description language, electronic design automation (EDA), and/or FPGA tools.
• Proficiency in electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture.
• Experience in executive written and verbal communication skills, mastery in English and local language.
• Ability to work with cross functional teams (DV/Arch/Design/FW) to identify coverage scope
• A strong knowledge of C/C++ or Python scripting 
• Experience with CPU or GPU systems, DDR memory and high-speed peripherals 
• Familiarity with verification environments e.g. UVM, System Verilog 

Qualifications: BS in Electrical Engineering with 6 Years of Experience

• Experience in verification preferably in communication systems
• Proven track record where products have gone to volume production, preferably 1st pass Silicon.
• Strong written and verbal skills
• Strong problem solving and debugging skills
• Strong proficiency in SystemVerilog, UVM, C, System C and good scripting skills.
• Experience with Verification techniques using Matlab/C/System reference models
• Able to adopt the use of new techniques and methodologies
• Experience in developing coverage-driven verification test plans.
• Familiarity with constrained random and assertion based verification
• Knowledge of CPU & SOC architecture/design & in-depth knowledge of verification flow.

Qualifications: BS in Electronics Engineering with 5 Years of Experience

• Non-internship professional software development experience
• Programming experience with at least one modern language such as Java, C++, or C# including object-oriented design
• Experience contributing to the architecture and design (architecture, design patterns, reliability and scaling) of new and current systems.
• Experience in semiconductor design verification experience
• Experience using System Verilog and UVM
• Experience in testbench development including: stimulus, checkers, assertions and coverage
• Experience using multiple verification platforms
• Experience with C/C++, Python, or Perl
• Experience verifying multiple levels of logic including: IP blocks and full SOC system testing
• Experience with formal verification
• Experience with embedded software

Qualifications: BS in Software Engineering with 2 Years of Experience