DESIGN VERIFICATION ENGINEER SKILLS, EXPERIENCE, AND JOB REQUIREMENTS

Published: Oct 23, 2024 - The Design Verification Engineer specializes in complex CPU and general computer architectures, blending proficient communication and teamwork skills to enhance diverse teams. Expertise encompasses verification principles, SystemVerilog, UVM/OVM, and advanced debugging in simulation environments. Develops and optimizes simulation, emulation, and FPGA verification environments, leveraging Agile practices and scripting in Python or C/C++.

Essential Hard and Soft Skills for a Standout Design Verification Engineer Resume
  • SystemVerilog
  • UVM/OVM
  • RTL Debugging
  • FPGA Programming
  • Assembly Language Programming
  • Python/C++ Scripting
  • Simulation and Emulation Tools
  • Testbench Design
  • Waveform Analysis
  • Verilog Proficiency.
  • Communication
  • Teamwork
  • Problem-Solving
  • Critical Thinking
  • Attention to Detail
  • Adaptability
  • Time Management
  • Innovation
  • Conflict Resolution
  • Leadership.

Summary of Design Verification Engineer Knowledge and Qualifications on Resume

1. BS in Electrical Engineering with 3 Years of Experience

  • Experience in: Computer architecture, Object Oriented Programming, Algorithms and Data Structures
  • Experience in networking
  • Experience in Verilog, SystemVerilog, VHDL
  • Experience in Perl or python
  • Experience in medical device verification
  • Able to effectively work in a team environment and interface well with other functions
  • Effective communicator with Good written and verbal communications skills
  • Ability to work in teams and collaborate effectively with people in different functions
  • Ability to take the initiative and drive for results
  • Good verbal and written English communication skills

2. BS in Computer Engineering with 5 Years of Experience

  • Experience in SoC Verification.
  • Advanced knowledge of SoC architecture/design & in-depth knowledge of verification flow.
  • Expected to have a deep understanding and shown experience in advanced verification process, including dynamic, coverage based and formal methods.
  • Familiarity with verification environments, VMM, SystemVerilog 
  • Knowledge of formal, hardware acceleration
  • Scripting and programming experience using several of the following: Perl, e, Verilog, SystemVerilog, C, C++, and TCL.
  • Hands on experience with SV and UVM
  • Hands on Experience with executable test plans and Coverage Driven verification
  • Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
  • Familiarity with C/C++
  • Experienced with verification methodology such as UVM/VMM/OVM.
  • Proven experience as a DV engineer

3. BS in Computer Science with 3 Years of Experience

  • Experience in designing or validating SoCs, CPUs, chipset or IP blocks. 
  • In depth knowledge of RTL language such as System Verilog or Verilog. 
  • In depth knowledge of industry standard tools and methods such as VCS, OVM/UVM and UPF. 
  • Preferred Qualifications Vast knowledge of object oriented programming in C++, Java, Python, or some other languages. 
  • Strong communication skills (written and verbal), tolerance of ambiguity, problem solving, teamwork, attention to detail, commitment to task, and quality focus. 
  • Experience with chip level power and reset operations. 
  • Knowledge in Agile development and familiar with Scrum process.
  • Should be a great teammate with excellent communication skills.
  • Experience with Signal processing 
  • Experience with Gate Level Simulation 

4. BS in Software Engineering with 8 Years of Experience

  • Verification experience in UVM
  • Ability to adapt to a start-up fast paced dynamic environment
  • Hands on experience with System Verilog constraints writing, structures and classes.
  • Hands on experience of executing multiple projects using UVM based SOC verification. 
  • Ability to create or enhance existing UVM sequences and tests. 
  • Knowledge of UVM constructs: uvm_sequence, uvm_phases, uvm_callback.
  • Ability to build or help in building user constraints based random verification infra-structure using UVM for block level and/or Chip level verification.
  • Strong understanding of waveform debugging, RTL simulation.
  • Ability to integrate third party Bus Functional Model, integrate it in the existing environment and build verification infra-structure on top of that.
  • Ability to write assertions, cover properties, cover points.
  • Ability to generate functional coverage, code coverage data and going through it with designers, driving the effort of closing the coverage holes and/or resolving them to closure with designers.
  • Experience with running Gate Level simulation.

5. BS in Systems Engineering with 6 Years of Experience

  • Proven verification experience on large ASIC development projects in a hardware development setting
  • Strong background in SystemVerilog and UVM verification methodologies
  • Strong debug skills and experience with debug tools such as DVE/Verdi
  • Proficiency in Object Oriented programming, computer architecture and data structures
  • Proficiency in behavioral modeling of analog IP for mixed-signal ASICs
  • Strong analytical/problem solving skills and pronounced attention to details
  • Strong interpersonal and communication skills
  • Help in test plan development for block and Chip level and driving it to closure by capturing test plan items in tests
  • Familiarity with basic synthesizable RTL designs (flops, fifos Clock domain crossing) 
  • Strong familiarity with any of these protocols: PCie, Ethernet (100G and above), DDR4.
  • Ability to create regression scripts to run individual and batch jobs on grid.

6. BS in Electrical Engineering with 4 Years of Experience

  • Experience in verification preferably in communication systems
  • Proven track record where products have gone to volume production, preferably 1st pass Silicon
  • Hands on experience in UVM, C, System C. and scripting
  • Experience in digital verification, preferably in communication systems
  • Familiarity with Matlab
  • Familiarity with formal verification techniques
  • Strong written and verbal skills
  • Excellent programming skills and knowledge of software engineering practices including object-oriented design.
  • Experience developing scalable and portable testbenches and components.
  • Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, gate level simulations.
  • Proficient in a scripting language such as Python or Perl.
  • Deep knowledge of System Verilog testbench language, DPI, and UVM.
  • Deep knowledge of System Verilog UVM and vertical testbench integration
  • Great debugging and problem solving skills.

7. BS in Computer Engineering with 5 Years of Experience

  • Experience in verification strategy development and execution for large SoCs and signoff with coverage metrics
  • Knowledge of UVM methodology, SystemC and System Verilog
  • Implementation of randomized and directed random testbenches for networking and multi-cpu environments
  • Knowledge of verification IP and functional coverage techniques
  • Experience with signoff of SoC designs with coverage metrics
  • Experience with gate level simulations of delay annotated netlists
  • Experience with PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment 
  • Experience with design 
  • Experience with Specman E language
  • Strong logical and creative problem-solving skills with excellent analytical and debugging skills
  • Must be a flexible self-starter who can ramp up with new technologies, products, etc.
  • Motivated, and able to work effectively under pressure
  • Good written and oral communication skills

8. BS in Computer Science with 4 Years of Experience

  • Strong communication, analytical and documentation skills and ability to interface with other groups.
  • VLSI functional verification experience, preferably with exposure to complex, high speed custom VLSI products
  • Strong C/C++ programming experience.
  • Verilog/SystemVerilog/UVM experience.
  • Familiar with shell scripts, perl or python.
  • Familiar with computer architecture or artificial intelligence
  • Experience or knowledge of SoC, ARM cores, AMBA bus, USB 2.0/3.0, PCIe gen2/3, and CPU peripherals.
  • Experience or knowledge of verification IP
  • Experience with the simulation and verification of a system including 3rd party IP
  • Experience using Cadence/Denali ViP

9. BS in Software Engineering with 3 Years of Experience

  • Experience with SystemVerilog with assertions, UVM test benches
  • Experience with using Vendor Verification IP, including PCIe ViP
  • Experience with chip-level verification of PCIe Endpoints
  • Experience with C and C++ and scripting languages
  • Experience with Linux environment
  • Familiarity with industry-standard ASIC EDA tools, including logic simulators, and debuggers
  • Familiarity with formal verification and linters
  • Excellent verbal and written English communication skills and the ability to interact professionally with a diverse group
  • Experience in any of the following: SystemVerilog, UVM, SystemC, Verilog or VHDL
  • Experience in C++/Python and Object-Oriented Methodology
  • Experience with DFT

10. BS in Systems Engineering with 6 Years of Experience

  • Experience working on pre- or post-silicon functional verification and validation of computing elements such as CPUs, GPUs or similarly complex verification environments using SystemVerilog or C++
  • Experience working on complex CPU architectures and general computer architectures
  • Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams
  • In depth knowledge of verification principles, testbenches, stimulus generation, SystemVerilog, UVM/OVM, and coverage
  • Extensive experience debugging RTL and SV using waveform viewers and HW/SW debuggers within a simulation environment
  • Assembly programming experience in industry standard ISAs
  • Proficient experience writing scripts/software with industry standard languages like Python or C/C++
  • Experience building and optimizing simulation, emulation, and/or FPGA verification environments, tools, flows, and methodologies
  • Experience with Agile software practices
  • Familiar with Verilog and System-Verilog

11. BS in Electrical Engineering with 3 Years of Experience

  • Exceptional analytical skills and problem solving skills.
  • Proficiency with at least one of these - C++, Object Oriented Programming, UVM, System Verilog.
  • Strong knowledge on basic concepts of CPU/SoC architecture.
  • Extraordinary analytical skills.
  • Ability to handle complex and hard-do-solve problems in programming and verification.
  • Ambitious and dedicated.
  • Good interpersonal skills.
  • Familiarity with test creation, logic simulation & debug.
  • Knowledge of Object Oriented programming.
  • Knowledge of scripting languages

12. BS in Computer Engineering with 4 Years of Experience

  • Experience in design verification, System Verilog, and UVM
  • Experience with scripting languages such as Perl and Python
  • Deep working knowledge of EDA verification tools
  • Preferred to have experience with C-level and ASM level programming/debug
  • Familiarity with Formal verification methodology/tool 
  • Experience with bus-protocol (i.e. AXI, OCP) and/or Networking/Ethernet protocol verification 
  • Strong time management skills that enable on-time project delivery
  • Working well in a team environment is imperative in this role.
  • Demonstrated ability to build strong, influential relationships
  • Good listener and excellent verbal and written communication skills

13. BS in Computer Science with 2 Years of Experience

  • Good understanding of the high-performance microprocessor architecture and complex server SoCs
  • Strong fundamentals and working knowledge of Cache coherence protocols, computer architecture.
  • Good verification experience, adept at UVM verification methodologies.
  • Good understanding of power consumption in design (leakage, dynamic, clock)
  • Expertise in supporting the emulation and the back-end integration teams.
  • Development experience in languages common to the industry
  • Exposure to different verification techniques such as x-prop, power-aware simulations
  • Understanding of the gate level simulation methodology
  • Working knowledge of AMBA/AXI protocols, while understanding of CHI 
  • Knowledge of power analysis tools (Primepower, Joules) and methodologies (0-delay, SDF, GLS)
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