• Identify important verification scenarios and create test plans
• Write test bench, monitor(s) and checker(s) by using constrained-random verification, SystemVerilog UVM, SVA, power-aware simulation or formal equivalence checking
• Identify and write all types of coverage measures
• Review and increase simulation coverage
• Setup regression environment and perform regression
• Architect, develop and maintain Test and Verification Systems for complex digital systems and IP components
• Wide-ranging, comprising multi-language software, HDL simulators and lab-based hardware.
• Devise verification strategies and implement test plans to ensure the delivery of high-quality, fault-free products.
• Worked in a Digital and Verification Development team contributing to the development and validation of complex digital mix signals for high-speed interface IP.
• Engage in verification activities under the supervision of more experienced personnel, and to exercise judgment to determine appropriate actions to achieve the required specifications.

Skills: Constrained-Random Verification, SystemVerilog and UVM Expertise, Simulation Coverage, Formal Verification, Regression Testing, Test System Architecture, Multi-Tool Proficiency, Mixed-Signal Verification

• Collaborate with other team members in a dynamic environment to define new technology requirements and specifications.
• Deliver detailed test plans for verification of complex digital design blocks.
• Create verification environments with SystemVerilog and UVM.
• Work closely with design engineers to create coverage measures and corner cases
• Identify design holes and deliver functionally correct blocks
• Perform synthesis, P&R and timing closure with FPGA vendor tools.
• Create and execute plans for platform bring-up, debug, and validation.
• Document and support test plans and reviews.
• Develop a comprehensive test environment for TSMC’s Die-to-Die Interconnect product family
• Work with the design team to verify the quality of the design prior to tape-out and customer delivery
• Build productive working relationships, mostly within the team.

Skills: Technology Requirements Collaboration, Test Plan Development, SystemVerilog and UVM, Coverage and Corner Cases, Design Debugging, FPGA Synthesis and Timing, Platform Validation, Test Plan Documentation

• Collaborate across teams to come up with creative solutions to challenges in verification and beyond
• Execute on block-level and top-level verification tasks
• Developing UVM test benches, creating test stimulus, debugging test results, creating and analyzing test coverage
• Create and improve automation tools and flows
• Help grow the verification team through mentorship and recruiting efforts
• Drive improvements to the verification methodology of the entire team
• Development of a top-level stimulus generation flow for Mythic's unique IPU architecture
• Prepare and present reports outlining the outcome of technical projects.
• Develop SystemVerilog/Verilog-AMS models for analog circuits and circuit blocks to enable efficient full chip functional verification.
• Create block and chip level test benches using UVM/SystemVerilog environment
• Participate in design verification by performing schematic/behavioral comparisons, writing assertions and debugging code

Skills: Creative Solution Collaboration, Block-Level and Top-Level Verification, UVM Test Benches and Debugging, Automation Tool Development, Team Mentorship and Recruitment, Verification Methodology Improvement, Top-Level Stimulus Generation, SystemVerilog/Verilog-AMS Modeling

• Learn and understand NXP design project verification requirements
• Work with the global Design Enablement team and with all major EDA vendors to develop and improve verification flows
• Support product design teams using verification tools and flow, diagnosis and problem solving, deployment of new tools and methods, training designers in using new verification tools and techniques
• Work with EDA vendors to implement new features required for advanced NXP designs
• Identify best practices, and disseminate them across the company
• Develop a verification environment, including all the respective components such as stimulus, checkers, assertions and coverage
• Work with designers to develop verification plans
• Execute verification plans, bring up DV environment, do regression testing, debug failures
• Help with post-silicon debugging and correlation
• Participate in applicable product/project reviews.

Skills: Verification Requirements Understanding, Collaboration with Design Enablement Team, Tool Deployment and Support, Feature Implementation with EDA Vendors, Best Practices Identification, Verification Environment Development, Verification Plan Execution, Post-Silicon Debugging

• Review the Design Specs of the assigned modules, understand features and in-system behavior
• Create or maintain a module Verification Plan
• Create or maintain the module Verification Specs, detailing every test case
• Write simulation scenario
• Implement, execute and debug the specified TCs
• Improve or propose improvements to the module Test-Bench, when necessary
• Analyze bugs reported from Simulations and/or Silicon Validation
• Proactively interact with Designers and System engineers to facilitate or improve any verification task
• Report the assigned activities status on a regular basis
• Participate to weekly meetings
• Exhibits regular, reliable, punctual and predictable attendance.

Skills: Design Specs Review, Verification Plan Creation, Test Case Specification, Simulation Scenario Writing, Test Case Execution and Debugging, Test-Bench Improvement, Bug Analysis, Cross-Functional Collaboration

• Strong skill with VCS/Verdi simulation tools, Formal verification tool (vc_formal)
• Knowledge of UPF, UVM(Universal Verification Methodology) and SVA (System-Verilog Assertion) is a plus
• Strong debug skills and demonstrated experiences in Perl /TCL/Python scripting is a plus
• Good English communication both verbally and in writing
• Great team player, willing to support others
• Self-motivated and highly enthusiastic about technology and solving problems
• Experience with Mixed-Signal SoC verification and real modeling of analog and mixed-signal blocks.
• Experience verifying protocols and spec compliance (e.g. I2C, UART, SPI, DisplayPort, CSI/DSI, PCIe).
• Experience with Cadence Virtuoso tools and Mixed-Signal Verification methodology and tools (AMS / APS / Flex)
• Experience with gate-level simulations/debug
• Experience with lab silicon bring-up, validation and production test support

Qualifications: BA in Electrical Engineering with 4 years of Experience

• Experience in developing UVM-based testbench infrastructure from the ground up, functional cover point development, code coverage analysis/closure and assertion development.
• Knowledge of AHB/AXI/APB protocols, and familiarity with verification of processor-based SoC designs
• SystemVerilog, C/C++, System C, TCL/Perl/Python/shell scripting.
• Excellent debugging and analytical skills.
• Able to work on assignments with minimal directions.
• Experience in Mixed-signal verification and analog modeling is a big plus.
• Experience in Power IC, DSP, and signal-chains
• Experience in RTL design/FPGA flow is a big plus.
• Experience or understanding of electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture.
• Good analytical and problem-solving skills.
• Understanding of design for VLSI components, integrated circuitry, architectures and algorithms.

Qualifications: BS in Computer Engineering with 3 years of Experience

• Knowledge of digital logic design and ASIC design flow
• Knowledge of image sensors or image data processing
• Experience with embedded microcontrollers or microprocessors such as ARM
• Experience with serial communication protocols such as SPI, I2C, I3C, or CSI
• Experience writing firmware or software using C or C++
• Experience with synthesis (i.e. Design Compiler), static timing analysis (i.e. PrimeTime), place and route, or power analysis
• FPGA design and verification experience
• Knowledge of programming and scripting, hardware description language, electronic design automation (EDA), and/or FPGA tools. Coursework in VLSI design or VLSI concepts.
• Good written and verbal communication skills
• Programming experience in C
• Experience writing scripts in languages such as Perl or Python
• Programming experience in C++ and assembly
• Experience defining coverage space and writing coverage model

Qualifications: BS in Software Engineering with 4 years of Experience

• Proven track record of taking several chips in from product definition to production.
• Good understanding of ASIC design and verification methodologies and flows.
• Solid understanding of standard ASIC verification techniques
• Experience with Test planning, Testbench creation
• Code and Functional coverageDirected and random stimulus generation
• Solid understanding of verification methodologies and one or more of the following standard testbench languages
• Experience with C/C++, Perl, Tcl scripting, Verilog PLI, SystemVerilog (OVM/UVM)
• Proficient in object-oriented programming.
• Experience in the development of re-usable VIP
• Experience in working with third-party VIP
• Experience with implementing constraint random verification methodology.
• Good problem-solving skills.

Qualifications: BA in Applied Mathematics with 5 years of Experience

• Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies
• Experience in crafting test bench environments for unit and system-level verification
• Expertise in System Verilog or similar HVL
• Strong debugging and analytical skills
• Perl and C/C++ programming language experience desirable
• Prior experience with arbiters, interconnect networks and/or caches is desirable
• Strong communication skills and ability and desire to work as a great teammate are huge plus.
• Experience with design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
• Strong software engineering skills including an understanding of object-oriented programming, data structures, algorithms and Assembly language for Arm or other architectures
• High-level understanding of CPU architecture and microarchitecture, including experience in the area of processor pipeline and memory systems
• Experience in the specification, creation, and debugging of System Verilog/UVM constrained-random test benches

Qualifications: BS in Systems Engineering with 4 years of Experience