• Leading the Synthesis and Timing of complex designs, providing guidance, and interfacing with the RTL team for quality RTL delivery
• Interfacing with internal and external teams including Design, IP, Library
• Working independently with the PNR and RTL design team on the Physical implementation and power intent requirements
• Develop smart power functional blocks and complete mixed-signal ASICs from definition to series maturity
• Analog/ mixed signal circuit definition, design and simulation
• Design layout and verification
• Support or execute product validation and debug activities working with Product, Quality and Test engineering up to production ramp-up 
• Generate design documentation reports and participate in Design Reviews
• Drive and/or support risk assessment, risk management and Design/Product FMEAs
• Drive and/or support the preparation of product-level verification and validation plans
• Contribute to Technology Process and Design Methodology improvements

Skills: Synthesis Leadership, Timing Closure, Physical Implementation, Power Planning, Mixed-Signal Design, Layout Verification, Product Validation, Risk Management

• According to the system specifications, able to build the analog component model, transistor-level circuit design, simulation and verification independently
• Complete the layout design independently
• Work closely with test engineers to finish the test of the analog circuits
• Participate in the preparation of technical documents for anilox circuits
• Design and verification of the IP and IC to ensure technical requirements
• Technical Lead in project teams on activities towards the introduction of new products to timelines defined within project plans
• Ensure that new product releases meet manufacturability, reliability, customer and market requirements in collaboration with product management, wafer process, assembly and test
• Provide project management and/or technical expertise for the team
• Assist the product management by providing technical support concerning specification and justification of new product developments, answering specific customer technical enquiries and complaints
• Develop appropriate levels of knowledge in associated areas of product development work, namely the product release process, systems, project management, product specification, simulation and design
• Develop subject matter knowledge and expertise in at least one area of R&D

Skills: Analog Modeling, Circuit Design, Layout Design, Circuit Testing, IP Verification, Project Leadership, Product Release, Technical Support

• Layout IC Design Engineer with specialization in CMOS Sensor, Analog/ Mixed Signal IC Design
• Design custom layout for analog and mixed signals ICs in 0.11um, 0.18um and 0.25um technology for imaging sensor and capacitive touch sensor IC
• Review schematics and interpret them into physical layout forms as well as run verification flows for sensor analog ICs
• Conduct thorough design reviews
• Collaborate with various groups during the design cycle including system, digital and analog design teams
• Own and responsible for the delivery of a specific unit on the chip
• Write high-performance and low-power RTL
• Work with verification to verify the correctness of the unit
• Work with implementation to achieve timing, area, performance, and power goals

Skills: CMOS Layout, Mixed-Signal Design, Schematic Interpretation, Design Review, Cross-Team Collaboration, Unit Ownership, RTL Writing, Timing Optimization

• Work with colleagues in the Systems team to help optimally partition the system solution and make the most cost-effective integration trade-offs
• Work with colleagues in the IC Design team to devise a chip architecture, refine it to the block level and agree on a chip floor plan
• Devise innovative circuit solutions that implement the complex and intellectually challenging functions and control schemes to deliver target system performance
• Capture his/her design in schematic form according to the methodology and quality standards developed and adopted by the design team
• Share responsibility for compact cell layout with specialist layout designers in the team
• Diligently employ best practice methods in analogue IC Design to ensure that first silicon behaves as intended and as simulated before tape out
• Avoid circuits or layouts that might be inadequately modelled in the process design kit
• Verify design correctness by comprehensive circuit simulations, including Monte Carlo methods
• Design circuits for testability and manufacturability, helping maximise yield and product margin
• Ensure that his/her circuits, when integrated in the complete chip with all its parasitics, deliver the performance over process, supply voltage and temperature
• Ensure that his/her circuits and layouts comply fully with the design rules (physical and electrical) of the process and its design kit
• Carry out detailed peer review of the circuits and layouts created by colleagues in the IC Design team, helping maintain the team’s first-time success rate
• Document his/her designs to the highest standards of clarity and completeness
• Identify opportunities for patenting innovative circuit techniques and document his/her inventions for patent drafting

Skills: System Partitioning, Chip Architecture, Circuit Innovation, Schematic Design, Cell Layout, Analog Simulation, Design Compliance, Peer Review

• High-level architecture specification analysis both interactive authoring and/or review
• Electronic design specification generation, including micro-architecture development
• High-quality, high-performance Verilog RTL implementation from design specification, including areas such as asynchronous clock domain crossings, multiple power domains, low-power design, and integrating third-party IP
• Working with cross-functional teams such as Firmware and Systems Engineering to deliver detailed testing strategies and usage models
• Concisely documenting the RTL code and the verification environment to reflect functionality
• Design of logic relating to the SAS, SATA, and PCIe specifications, as well as general datapath function coding
• Lab support of the chip as it progresses through validation
• Work as part of a physical design team implementing chips from netlist to GDSII
• Responsible for chip floor planning, designing partitions and block pin assignments on multi-million gate designs
• Perform blocks' automatic place and route (APR), timing closure, physical verification, IR/EM (electro-migration) analysis
• Work on chip assembly and timing verification
• Work on script development to make the physical design flow more efficient

Skills: Architecture Analysis, RTL Design, Clock Domain, IP Integration, Test Strategy, Lab Validation, Physical Design, Flow Scripting

• Deep understanding of analog/mixed-signal design
• Solid understanding and experience of crafting analog mixed signal circuit blocks including ADCs, DACs, PLLs, DLLs, filters, bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits and oscillators
• In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
• Experience with high-speed digital circuits (e.g., serializer, de-serializer, counters, dividers, etc.)
• Design experience in sophisticated CMOS technologies, design with FinFET technology
• Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization
• Experience in lab testing of mixed-signal circuits 
• Experience in using spectrum analyzers, oscilloscopes, signal generators, etc., to validate analog designs
• Able to build VerilogA/AMS behavioral models
• Able to analyze and lead characterization data from lab and volume testing

Qualifications: BS in Semiconductor Engineering with 7 years of Experience

• Curious about emerging technologies and motivated to find new solutions to improve the existing tech infrastructure
• Able to be an analog-oriented circuit designer, excited about working on a full-chip design
• Experience with analog (full-custom, transistor-level VLSI) design within a UNIX environment
• Proficient with schematic capture tools such as Cadence Virtuoso or Synopsys Custom Compiler
• Familiar with Spectre and/or other Spice-based circuit simulators such as Hspice, XA, Finesim or AFS
• Decent knowledge of the design flow, testing methodology, block-level specifications, calibration and compensation, etc.
• Familiar with the layout design concepts (parasitic effects, symmetry, regularity and matching, gradient and proximity effects, reliability, etc.)
• Experience using scripting languages (Shell, PERL, Python, TCL, etc.)
• Experience with analog circuit modeling in Verilog or VerilogA
• Experience with MATLAB and Simulink

Qualifications: BS in Analog Circuit Design with 8 years of Experience

• Experience leading analogue top-level integration/verification
• History of successfully leading multiple IPs/sub-systems to mass production
• Experience with Continuous and Discrete Time Delta Sigma architectures, including Class D architectures
• Matlab/Simulink system analysis background to help the team define/validate architecture and analyze trade-offs
• Solid mixed-mode design experience leading complex design projects, integrating analogue and digital designs
• Experience with CMOS analog circuit design
• Good documentation and communication skills and the ability to work independently and with others in a distributed environment with engineers in several locations
• Demonstrate a true motivation to work with a team to bring new ideas in the audio domain that will help to surpass the competitive landscape
• Strong willingness to provide innovative circuit design solutions
• Ability to mentor other engineers in the state-of-the-art
• Good knowledge and advanced analytical and/or technical interpretation to resolve a variety of complex problems
• Experience with AMS/System-Verilog modeling for mixed-signal verification
• Experience in the design of sigma-delta ADCs/DACs from system analysis to implementation
• Must have strong analytical skills
• Experience with Cadence EDA tools
• Experience in the use of SPICE or Spectre simulation
• Excellent verbal and written communication skills
• Experience in using diverse laboratory tools for silicon evaluation
• Experience with a Linux workstation environment

Qualifications: BS in Semiconductor Engineering with 11 years of Experience

• Experience with DSP fundamentals and FPGA implementation
• Experience with MATLAB/Simulink
• Experience with microchip EDA tools and flow (Synopsys, Cadence)
• Experience in leading a design team
• Experience in hardware design and hands-on lab debugging
• Experience with UVM/SystemVerilog
• Experience with generating scripts (Perl, Tcl, Python)
• Strong written and oral communication skills
• Ability to mentor and willingness to be mentored
• Strong debugging and problem-solving skills
• Ability to distill higher-level requirements into micro-architecture
• Experience with a designer-level test bench (VHDL or SystemVerilog)
• Familiarity with revision control (git, CVS, ClearCase, etc.)
• Working knowledge of internal logic analyzer (ILA/chipscope/signaltap)
• Experience and willingness for lab testing
• Current Security Clearance (Secret), or eligibility to obtain one
• Working knowledge of C/C++
• Experience with interfaces such as ADC/DACs, SERDES, PCIe, JTAG, DDRx

Qualifications: BS in Electronic Systems Design with 9 years of Experience

• Excellent communication skills and ability to work with a cross-functional, distributed team
• Experience using Cadence mixed signal/analog design flow
• Experience with high-speed/RF electronics design
• Experience with high-speed/RF measurements and/or signal integrity
• Experience with high-speed serial link communication
• Experience with video interfaces and data converters
• Strong background in analog/mixed-signal circuits for RF and wireline applications
• Solid understanding of CMOS process and device physics
• Knowledge of RF systems modeling and analysis
• Strong written and verbal communication skills

Qualifications: BS in Signal Processing with 6 years of Experience