• Translating the product definition into design specs
• Work with Analog and Digital team to define design architecture
• Create microarchitectures to meet the system and chip spec
• Proactively identify risks and drive solutions to mitigate them
• RTL development and verification (RTL and Gate level)
• Static timing constraint generation and analysis/signoff
• Define and drive test and validation methods
• Lab evaluation and silicon debugging on new designs
• Contribute to RTL design and verification flow improvement strategies.

Skills: Design Specification Translation, Architecture Definition, Microarchitecture Creation, Risk Mitigation, RTL Development, Timing Analysis, Test Methodology Design, Silicon Debugging

• Work with stakeholders and others in a multidisciplinary team of electrical, firmware, and mechanical engineers in a development environment to define requirements and develop solutions.
• Develop logic for ASIC applications.
• Verify designs using simulation tools.
• Generate and support accurate timing constraints.
• Support of system engineering activities
• Support of the project management in all design-related topics
• Definition and support in the procurement of test samples
• Presentation of the design to the customer
• Support of the validation technique in the creation of validation procedures
• Carrying out and supporting customer reviews
• Collaborate with the digital implementation team to optimize the quality of results (area and power)

Skills: Requirements Definition, ASIC Logic Development, Design Simulation, Timing Constraints Management, Project Management Support, Test Sample Procurement, Design Presentation, Validation Technique Support

• Build and support the verification process of CMOS chips and components at block and chip levels
• Create simplified models of analog blocks to speed up preparation for chip tape-outs
• Take part in digital design, design, and verification automation process development
• Own the modeling and verification of chips
• Contribute to other projects as needed by management
• Develop microarchitecture and Verilog RTL implementation of complex digital blocks used in motion sensor ASICs
• Collect and analyze block requirements from other team members 
• Interface with DV engineers for any spec clarifications, communicating verification requirements, responding promptly to any reported bugs, and completing full coverage
• Develop constraints to be used during synthesis and timing analysis of the block, and during its integration at the ASIC level
• Analyze chip-level timing, area, and power reports for technical correctness, and possible improvements
• Constantly assess and drive efficiency and automation of the design flows
• Developing the specification, microarchitecture, and RTL design of modules as per requirements
• Work closely with the verification team for complete verification closure for both RTL and Gate level netlists

Skills: CMOS Verification, Analog Modeling, Digital Design Automation, Microarchitecture Development, Verilog RTL Implementation, Synthesis Constraint Development, Design Flow Efficiency, Verification Collaboration

• Top-level digital architecture planning including partitioning
• Collaborate with analog engineers to define the mixed-signal interface(s)
• Design for the test including scan insertion, test pattern generation, and fault grading
• Participate in chip and block level test planning with the DV team, help analyze the test results
• Overseeing automatic cell place and route
• Collaborate with the ADI design community on best practices
• Help the physical verification team evaluate the silicon, help production test engineers integrate ATPG patterns
• Help Application Engineers support the customer applications
• Sign-off checks such as lint and clock domain crossing analysis
• Implementation of Design for Test IP such as Memory BIST and Scan Test
• Support of post-silicon debug activities

Skills: Digital Architecture Planning, Mixed-Signal Interface Design, Design for Test, Test Planning and Analysis, Automated Place and Route, Best Practices Collaboration, Physical Verification Support, Post-Silicon Debugging

• Review and understand the design requirements and specifications
• Create, together with Digital Designers and SoC Architects, a verification plan
• Complete and review the plan with details about execution priority and effort estimations
• Execute the plan, at Block and/or SoC level, creating ad-hoc test-benches and simulation models or updating the existing ones
• Code the expected test-cases and assertions
• Interact with peers, designers, and architects for a quick analysis and resolution of all found bugs
• Complete the verification execution with Code Coverage analysis and final reports
• Maintain and develop the verification environment across the different projects, proposing improvements to the methodology, ways of working, team praxis and tool-chain
• Keep yourself updated with the latest verification methodology updates by following courses, seminars, webinars, and literature.

Skills: Verification Planning, Test-Bench Creation, Simulation Modeling, Test Case Coding, Peer Collaboration, Bug Resolution, Code Coverage Analysis, Verification Environment Maintenance

• Design experience in transistor-level and system level mixed-signal design
• Bitcoin-related experience 
• Excellent problem-solving, organizational, and analytical skills 
• Experience in design with Cadence Spectre, SpectreRF, AMS, and Virtuoso.
• Strong knowledge of Verilog-A & Matlab for system modeling and verification.
• Understanding of digital ASIC design and design flow
• Experience with high-volume IC manufacturing 
• Broad expertise in ASIC design, such as PLL, memory, IP integration
• Experience as technical lead, driving all aspects of ASIC projects including IC design, digital design, embedded FW, verification, and silicon validation.

Qualifications: BS in Electrical Engineering with 6 Years of Experience

• Digital design experience in complex multi-million gate architectures and deep sub-micron technologies.
• Solid understanding of crypto algorithms and standard methodologies
• Understanding various standards 
• Good foundation on theoretical security models/architecture & solutions for cryptographic protocols
• Able to work with multi-functional teams within Apple and external vendors across geographical boundaries to resolve architectural and implementation challenges with an eye towards schedule.
• Experience with multiple tape-outs with a majority of the tape-outs reaching MP with first silicon.
• Proven knowledge of high-level programming languages
• Hands-on experience with FPGA emulation, silicon bring-up, characterization, and debug
• Experience in algorithm development and signal processing data-path design
• Experience with mixed signal design 
• Expertise in Clock Domain Crossing design and verification techniques

Qualifications: BS in Computer Engineering with 10 Years of Experience

• Understanding of PLL concepts, experience with developing Digital PLLs
• Strong digital fundamentals (clock switching and gating, synchronization, serial interfaces, Lint and CDC analysis)
• Experience with synthesis, constraints, and timing closure
• Familiarity with verilog and system for design
• Simulation Debug capability
• A thorough understanding of digital logic design flow from spec and RTL development through PnR
• Familiarity with the Verilog language and simulators
• Good understanding of analog functionality and exposure to analog IC design methods
• Ability to work closely with Analog Design, Systems, and Apps teams in a coordinated effort to overcome technical challenges

Qualifications: BS in Electronics Engineering with 8 Years of Experience

• Fluency with ‘C’, ‘C++’, Python and basic knowledge in Verilog, System Verilog, or VHDL
• Good knowledge of Object Oriented Programming concepts
• Communications standards/framing structure are highly desirable (IEEE, Ethernet protocols)
• Ability to work independently as well as in teams
• Ability to work across functions and levels
• Experience in architectural design and implementation in VLSI or FPGA is desirable
• Basic knowledge of standard verification methods (ie UVM), regression and test
• Creative design ability to solve problems demanding the highest levels of speed
• Good English communication skills (verbal and written)

Qualifications: BS in Computer Science with 4 Years of Experience

• Knowledge of foundational electrical engineering, computer architecture and digital design concepts.
• Experience in digital design with FPGA and SoC devices.
• Development experience with Xilinx devices and design suite, such as Vivado, SDK and Vitis.
• Expertise in VHDL and/or Verilog.
• Experience developing MCU and SoC software in the C/C++ programming language.
• Working knowledge of modern FPGA architectures and external interfaces, including high speed converters, DDR RAM, and Solid State NAND and NOR based storage.
• Familiarity with standard physical layers for digital communication (UART, SPI, LVDS).
• Comfortable working in a dynamic and fast-paced development environment.
• Capable of creating Linux kernels to be deployed on Xilinx devices.
• Knowledge of digital communication systems and modulations (QPSK, 8-PSK).
• Experience developing FPGA based hardware for the space environment.

Qualifications: BS in Digital Design with 6 Years of Experience