Daniel Carter

Austin, TX

(512) 555-1843

daniel.carter@email.com

https://www.linkedin.com/in/danielcarter

SUMMARY

Results-driven Logic Design Engineer with 2+ years of experience in RTL design, static timing analysis, and SoC integration within the semiconductor industry. Proven record of achieving 99% timing signoff accuracy across multi-corner synthesis runs and improving simulation coverage by 28%. Expertise in SystemVerilog development and CDC analysis to optimize verification cycles, mitigate silicon re-spin risk, and drive measurable design quality improvements.

SKILLS

Verilog Coding

Static Timing Analysis

Clock Domain Crossing

Logic Synthesis

Gate-Level Simulation

Power Estimation

EXPERIENCE

Logic Design Engineer

SiliconCore Technologies, Austin, TX

June 2023 – Present

• Develop synthesizable RTL in SystemVerilog for CPU subsystems, enabling integration across 3 SoC blocks and achieving first-pass lint compliance.
• Perform static timing analysis and constraint validation, closing 97% of critical paths before final signoff.
• Execute CDC and LINT checks, eliminating 85+ violations and reducing functional escape risk by 22%.
• Support full-chip simulation and debug, improving regression pass rates to 98.5% within two release cycles.

Digital Design Intern

NanoChip Systems, Dallas, TX

May 2022 – August 2022

• Implemented RTL modules for arithmetic logic blocks, reducing synthesis area utilization by 14%.
• Automated verification scripts, accelerating regression runtime by 31%.
• Conducted gate-level simulations, achieving 99% functional alignment with RTL models.

EDUCATION

Bachelor of Science in Electrical Engineering

University of Texas at Austin

May 2023

Olivia Martinez

San Jose, CA

(408) 555-7721

olivia.martinez@email.com

https://www.linkedin.com/in/oliviamartinez

SUMMARY

Results-driven Logic Design Engineer with 5+ years of experience in CPU micro-architecture, DFT implementation, and timing closure within high-performance semiconductor environments. Proven record of achieving 98% structural test coverage and reducing timing violations 35% across multi-mode, multi-corner scenarios. Expertise in SDC constraint development and synthesis optimization to optimize design convergence, mitigate power-performance tradeoff risks, and drive measurable silicon readiness outcomes.

SKILLS

Scan Architecture

SDC Constraint Development

Fault Coverage Analysis

Power-Aware Design

Mixed-Signal Integration

Formal Verification

EXPERIENCE

Logic Design Engineer

NextWave Semiconductor, San Jose, CA

March 2021 – Present

• Architect RTL for CPU execution units, enabling frequency scaling improvements of 18% while maintaining power budgets.
• Lead synthesis and timing closure across 5 IP blocks, converging 100% signoff across multi-corner scenarios before tapeout.
• Implement DFT strategies and fault simulation flows, increasing structural coverage from 91% to 98.4%.
• Collaborate with physical design and verification teams, cutting ECO cycles by 27% through early constraint refinement.

Logic Design Engineer

Pinnacle Micro Devices, Fremont, CA

July 2018 – February 2021

• Designed SoC subsystems in Verilog, supporting integration of 12+ IP modules into mixed-signal platforms.
• Resolved 120+ CDC violations, improving cross-domain robustness and reducing post-silicon debug incidents 24%.
• Optimized scan timing flows, shortening closure cycles by three weeks per release.

EDUCATION

Bachelor of Science in Electrical Engineering

San Jose State University

May 2018

Michael Thompson

Santa Clara, CA

(669) 555-9024

michael.thompson@email.com

https://www.linkedin.com/in/michaelthompson

PROFESSIONAL SUMMARY

Results-driven Logic Design Engineer with 12+ years of experience in CPU architecture, SoC subsystem development, and power management logic within advanced-node semiconductor programs. Proven record of achieving 20% performance uplift across custom processor designs and delivering 99% timing signoff compliance before fabrication. Expertise in micro-architecture definition and multi-corner timing closure to optimize silicon scalability, mitigate re-spin risk, and drive measurable enterprise-level product outcomes.

CORE SKILLS

Full-Chip Timing Closure

Low-Power Methodologies

DFT Strategy Development

SoC Subsystem Integration

Power-Thermal Management

Cross-Functional Execution

EXPERIENCE

Logic Design Engineer

Vertex Computing Systems, Santa Clara, CA

January 2019 – Present

• Lead micro-architecture and RTL development for next-generation CPU cores, driving 22% performance gains across enterprise compute workloads.
• Direct synthesis and timing closure for 15+ high-performance blocks, achieving 100% multi-mode signoff before tapeout.
• Define power and thermal management logic, reducing dynamic power consumption 17% under peak workloads.
• Coordinate cross-functional teams spanning verification, physical design, firmware, and post-silicon validation, cutting bring-up cycles by 30%.

Logic Design Engineer

Apex Silicon Solutions, Mountain View, CA

June 2013 – December 2018

• Architected SoC subsystems supporting deep learning accelerators, enabling 25% throughput improvements in mixed-signal IC platforms.
• Implemented enterprise DFT and fault simulation methodologies, raising coverage to 99% across large-scale designs.
• Mentored 8 engineers while standardizing timing constraint flows, accelerating closure convergence by 34%.

EDUCATION

Master of Science in Electrical Engineering

Stanford University

June 2013

• Lead full-chip digital development across interdisciplinary R&D programs, defining micro-architecture and product specifications for high-speed, power-efficient silicon platforms delivering first-pass functional readiness across complex enterprise applications.
• Architect robust block-level designs in SystemVerilog, implementing synthesizable RTL across multi-million gate environments and accelerating integration milestones within aggressive tapeout schedules.
• Orchestrate CDC analysis, lint, DFT insertion, synthesis, and timing closure for advanced process nodes, resolving cross-domain violations and achieving signoff across 100% critical paths before fabrication.
• Collaborate with analog and mixed-signal engineering teams to develop calibration algorithms and behavioral models, expanding simulation coverage and strengthening correlation between pre-silicon validation and lab characterization.
• Direct verification planning and execution with cross-functional stakeholders, overseeing block and system-level simulations, plus formal methods to reduce debug iterations and compress validation cycles by multiple weeks.
• Coordinate silicon bring-up, test strategy, and performance characterization with laboratory and systems teams, documenting compliance against critical specifications while mentoring junior engineers within a multi-disciplinary engineering organization.

Core Skills:

• RTL Design
• SystemVerilog
• CDC Analysis
• Timing Closure
• Formal Verification
• DFT Implementation

• Drive micro-architecture development and RTL implementation of complex IPs and SoC subsystems in partnership with Systems and Architecture teams, enabling seamless integration across multi-block silicon programs.
• Define clocking, reset, power domains, and pin multiplexing strategies at the chip level, aligning integration frameworks across enterprise-scale SoC platforms and minimizing downstream rework during assembly.
• Execute comprehensive LINT and CDC quality assessments on delivered RTL, documenting waivers and exceptions to achieve 100% rule compliance before synthesis readiness.
• Lead synthesis, constraint development, equivalence checking, and timing closure for implemented IPs, converging signoff across multi-corner scenarios and consistently meeting target frequency specifications.
• Produce structured implementation documentation following systematic design reviews, strengthening cross-functional transparency and accelerating verification handoff across geographically distributed engineering teams.
• Advance cycle-time and quality improvement methodologies throughout the development lifecycle, collaborating across verification and integration groups to streamline delivery from specification through silicon validation.

Core Skills:

• Micro-Architecture Design
• RTL Implementation
• Clock Domain Crossing
• Timing Closure
• Power Domain Design
• Equivalence Checking

• Engineer logic design and verification for novel deep learning accelerators, advancing from architectural concept through RTL implementation and enabling integration into high-performance mixed-signal integrated circuits.
• Architect digital subsystems in Verilog and SystemVerilog, performing RTL, gate-level, and behavioral modeling across multi-million gate designs to achieve first-pass synthesis readiness.
• Execute synthesis, static timing analysis, CDC validation, power assessment, and floor planning, closing timing across multi-mode corners while meeting target frequency and power budgets.
• Conduct full-chip digital and mixed-signal simulations in collaboration with architecture, analog, verification, and physical design teams, strengthening cross-domain alignment throughout complex SoC programs.
• Deliver comprehensive design specifications, structured documentation, and formal review packages, reducing downstream integration issues and improving design traceability across cross-functional stakeholders.
• Lead hands-on lab evaluation, silicon characterization, and post-silicon debug, accelerating root-cause isolation and stabilizing production readiness within compressed bring-up schedules.

Core Skills:

• Deep Learning Accelerators
• RTL Design
• Static Timing Analysis
• Clock Domain Crossing
• Power Analysis
• Mixed-Signal Integration

• Create mixed-signal timing constraints and DFT logic SDCs within enterprise semiconductor programs, enabling accurate static timing signoff and supporting production-ready test architectures.
• Execute AMD-defined test coverage analysis and fault simulation methodologies, elevating structural coverage to target thresholds exceeding 98% across complex digital subsystems.
• Develop and refine scan timing flows, constraint generation, CDC waiver strategies, and violation debugging processes, reducing closure iterations by multiple tapeout cycles.
• Drive cross-functional issue resolution with verification, analog, and physical design teams, independently converging timing-related risks and delivering cost-effective solutions under aggressive schedules.
• Design arithmetic logic blocks using CMOS and proprietary standard cells, achieving target Power, Performance, and Area metrics across high-performance mixed-signal platforms.
• Lead customer requirement engagements and implement RTL through synthesis, DFT insertion, timing closure, and IP integration, aligning feature delivery with release and continuous integration processes.

Core Skills:

• SDC Constraint Development
• Design For Test
• Fault Simulation
• Static Timing Analysis
• RTL Implementation
• Arithmetic Logic Design

• Direct end-to-end design execution planning aligned with program milestones, orchestrating micro-architecture definition and documentation for SoC and subsystem development within large-scale CPU initiatives.
• Define and document next-generation CPU micro-architecture, including decoder, out-of-order scheduler, and execution units, ensuring architectural alignment across cross-functional engineering organizations.
• Lead synthesis and timing closure for multiple high-performance processor blocks, converging multi-corner signoff while meeting aggressive frequency targets in advanced process nodes.
• Guide a team of design engineers in implementing RTL for custom CPU logic, partnering with architects and verification teams to achieve specification compliance across complex compute pipelines.
• Collaborate with physical design, DFT, software, and post-silicon validation teams to optimize power-performance-area tradeoffs and accelerate silicon bring-up and debug cycles.
• Mentor junior engineers and interns within the Core Logic Design organization, strengthening technical depth and fostering a collaborative culture across multidisciplinary development environments.

Core Skills:

• CPU Micro-Architecture
• RTL Development
• Timing Closure
• Synthesis Optimization
• SoC Integration
• Post-Silicon Debug

• Establish leadership within the Power architecture team for a custom CPU core, driving feature architecture, IP microarchitecture, RTL implementation, synthesis, and power optimization across enterprise processor programs.
• Define and implement power, thermal, and telemetry management circuitry, contributing to HAS and MAS specifications while improving energy efficiency under sustained high-performance workloads.
• Collaborate with architecture, verification, firmware, and thermal engineering teams to deliver complex hardware systems, balancing modularity, scalability, DFX requirements, and power-performance-area tradeoffs.
• Execute SystemVerilog RTL development, validation, synthesis, and timing closure for multiple CPU subsystems, achieving signoff across multi-mode, multi-corner scenarios in advanced nodes.
• Provide technical governance across assigned modules, issuing risk-mitigated status reporting and ensuring 100% process compliance during design reviews and escalation management.
• Mentor and develop junior engineers while managing technology execution within projects, elevating team productivity, and strengthening technical depth across cross-functional CPU development initiatives.

Core Skills:

• Power Architecture
• CPU Microarchitecture
• SystemVerilog RTL
• Timing Closure
• Thermal Management Logic
• Design For Excellence